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参数资料
| 型号： | MC10H642FN |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 68030/040 PECL-TTL CLOCK DRIVER |
| 中文描述： | 10H SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 1/9页 |
| 文件大小： | 195K |
| 代理商： | MC10H642FN |
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 4
Motorola, Inc. 1996
9/96
The MC10H/100H642 generates the necessary clocks for the 68030,
68040 and similar microprocessors. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of part–to–part
skew, within–part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced to
+5.0V) for the input clock. TTL clocks are typically used in present MPU
systems. However, as clock speeds increase to 50MHz and beyond, the
inherent superiority of ECL (particularly differential ECL) as a means of
clock signal distribution becomes increasingly evident. The H642 also
uses differential PECL internally to achieve its superior skew
characteristic.
The H642 includes divide–by–two and divide–by–four stages, both to
achieve the necessary duty cycle skew and to generate MPU clocks as
required. A typical 50MHz processor application would use an input clock
running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz
(see Logic Diagram).
The 10H version is compatible with MECL 10H
ECL logic levels,
while the 100H version is compatible with 100K levels (referenced to
+5.0V).
Generates Clocks for 68030/040
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single +5.0V Supply
Function
Reset(R):
Select(SEL):
LOW on RESET forces all Q outputs LOW.
LOW selects the ECL input source (DE/DE).
HIGH selects the TTL input source (DT).
The H642 also contains circuitry to force a stable input state of the ECL differential input pair, should both sides be left open. In
this Case, the DE side of the input is pulled LOW, and DE goes HIGH.
Power Up:
The device is designed to have positive edges of the
÷
2 and
÷
4 outputs synchronized at Power Up.
1
VT
VT
Q1
GT
GT
Q0
VT
GT
GT
Q6
Q7
VT
SEL
5
6
7
8
9
10
11
25
24
23
22
21
20
19
Q5
Pinout: 28–Lead PLCC
(Top View)
VBB
DE
DE
VE
R
GE
DT
Q4
VT
VT
Q3
GT
GT
Q2
4
3
2
28
27
26
18
17
16
15
14
13
12
68030/040
PECL–TTL CLOCK
DRIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
4
5
11
26
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC10H642FNG | 功能描述:时钟驱动器及分配 BBG ECL/TTL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MC10H642FNR2 | 功能描述:时钟驱动器及分配 ECL/TTL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MC10H642FNR2G | 功能描述:时钟驱动器及分配 BBG ECL/TTL Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| MC10H643FN | 功能描述:转换 - 电压电平 5V ECL to TTL 1:8 RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
| MC10H643FNG | 功能描述:转换 - 电压电平 5V ECL to TTL 1:8 Clock Driver RoHS:否 制造商:Micrel 类型:CML/LVDS/LVPECL to LVCMOS/LVTTL 传播延迟时间:1.9 ns 电源电流:14 mA 电源电压-最大:3.6 V 电源电压-最小:3 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:MLF-8 |
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