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| 型号： | MC10XS3412DPNAR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 29/55页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH HIGH SIDE QUAD 24QFN |
| 标准包装： | 1,200 |
| 类型： | 高端开关 |
| 输出数： | 4 |
| Rds（开）： | 2 x 10 毫欧，2 x 12 毫欧 |
| 内部开关： | 是 |
| 电流限制： | 5A |
| 输入电压： | 4 V ~ 28 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-PowerQFN |
| 供应商设备封装： | 24-PQFN（12x12） |
| 包装： | 带卷 (TR) |
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FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FAIL SAFE MODE
The 10XS3412 is in Fail Safe mode when:
? V PWR is within the normal voltage range,
? wake-up = 1,
? fail = 1,
? fault = 0.
Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or IN_ON[0:3] or
RST input pin transitions from logic [0] to logic [1]. The WAKE
input is capable of being pulled up to VPWR with a series of
limiting resistance limiting the internal clamp current
according to the specification.
The watchdog timeout is a multiple of an internal oscillator .
As long as the WD bit (D15) of an incoming SPI message is
toggled within the minimum watchdog timeout period
(WDTO), the device will operate normally.
Fail Safe conditions
If an internal watchdog timeout occurs before the WD bit
for FSI open ( Table 9 ) or in case of V DD failure condition
(V DD < V DD(FAIL) )) for VDD_FAIL_en bit is set to logic [1], the
device will revert to a Fail Safe mode until the WD bit is
written to logic [1] (see Fail Safe to Normal mode transition
paragraph) and V DD is within the normal voltage range.
Table 9. SPI Watchdog Activation
Typical RFSI ( ? ) Watchdog
0 (shorted to ground) Disabled
(open) Enable
During the Fail Safe mode, the outputs will depend on the
corresponding input. The SPI register content is reset to their
default value (except POR bit) and fault protections are fully
operational.
The Fail Safe mode can be detected by monitoring the NM
bit is set to [0].
NORMAL & FAIL SAFE MODE TRANSITIONS
Transition Fail Safe to Normal mode
To leave the Fail Safe mode, V DD must be in nominal
voltage and the microcontroller has to send a SPI command
with WDIN bit set to logic [1] ; the other bits are not
considered. The previous latched faults are reset by the
transition into Normal mode (autoretry included).
Moreover, the device can be brought out of the Fail Safe
mode due to watchdog timeout issue by forcing the FSI pin to
logic [0].
Transition Normal to Fail-Safe mode
To leave the Normal mode, a Fail-safe condition must
occurred (fail=1). The previous latched faults are reset by the
transition into Fail-safe mode (autoretry included).
FAULT MODE
The 10XS3412 is in Fault mode when:
? V PWR and V DD are within the normal voltage range
? wake-up = 1
? fail = X
? fault=1
This device indicates the faults below as they occur by
driving the FS pin to logic [0] for RST input is pulled up:
? Overtemperature fault
? Overcurrent fault
? Severe short-circuit fault
? Output(s) shorted to VPWR fault in OFF state
? Open load fault in OFF state
? Overvoltage fault (enabled by default)
? Undervoltage fault
The FS pin will automatically return to logic [1] when the
fault condition is removed, except for overcurrent, severe
short-circuit, overtemperature and undervoltage which will be
reset by a new turn-on command (each fault_control signal to
be toggled).
Fault information is retained in the SPI fault register and is
available (and reset) via the SO pin during the first valid SPI
communication.
The Open load fault in ON state is only reported through
SPI register without effect on the corresponding output state
(HS[x]) and the FS pin.
START-UP SEQUENCE
The 10XS3412 enters in Normal mode after start-up if
following sequence is provided:
? VPWR and VDD power supplies must be above their
undervoltage thresholds,
? generate wake-up event (wake-up=1) from 0 to 1 on
RST. The device switches to Normal mode with SPI
register content is reset (as defined in Table 11 and
after 50 ? s typical and all SPI registers are set to default
values (set to logic [0]). The UV fault is reported in the
SPI status registers.
And, in case of the PWM module is used (PWM_en bit is
set to logic [1]) with an external reference clock:
? apply PWM clock on IN0 input pin after maximum
200 ? s (min. 50 ? s).
If the correct start-up sequence is not provided, the PWM
function is not guaranteed.
10XS3412
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
29
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| MC10XS3412JHFK | 制造商:Freescale Semiconductor 功能描述:SWITCH, QUAD, HS; Power Load Switch Type:Quad High Side; Input Voltage:5.5V; No. of Pins:24; Thermal Protection:Yes; On / Enable Input Polarity:Active Low; No. of Outputs:4; Operating Temperature Min:-40C; Operating Temperature ;RoHS Compliant: Yes |
| MC10XS3412JHFKR2 | 功能描述:电源开关 IC - 配电 RoHS:否 制造商:Freescale Semiconductor 输出端数量: 开启电阻（最大值）: 开启时间（最大值）: 关闭时间（最大值）: 工作电源电压: 电源电流（最大值）: 最大工作温度: 安装风格: 封装 / 箱体: |
| MC10XS3412KHFKR2 | 功能描述:电源开关 IC - 配电 RoHS:否 制造商:Freescale Semiconductor 输出端数量: 开启电阻（最大值）: 开启时间（最大值）: 关闭时间（最大值）: 工作电源电压: 电源电流（最大值）: 最大工作温度: 安装风格: 封装 / 箱体: |
| MC10XS3425EK | 功能描述:电源开关 IC - 配电 SPQL1025 RoHS:否 制造商:Exar 输出端数量:1 开启电阻（最大值）:85 mOhms 开启时间（最大值）:400 us 关闭时间（最大值）:20 us 工作电源电压:3.2 V to 6.5 V 电源电流（最大值）: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOT-23-5 |
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