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参数资料
| 型号： | MC12429FA |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封装： | LQFP-32 |
| 文件页数： | 1/9页 |
| 文件大小： | 173K |
| 代理商： | MC12429FA |
352
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Freescale Semiconductor, Inc.
TECHNICAL DATA
Order number: MC12429
Rev 7, 06/2001
High Frequency Clock Synthesizer
The MC12429 is a general purpose synthesized clock source. Its internal
VCO will operate over a range of frequencies from 200 to 400MHz. The
differential PECL output can be configured to be the VCO frequency divided by
1, 2, 4, or 8. With the output configured to divide the VCO frequency by 1, and
with a 16.000MHz external quartz crystal used to provide the reference
frequency, the output frequency can be specified in 1MHz steps. The PLL loop
filter is fully integrated so that no external components are required. The output
frequency is configured using a parallel or serial interface.
Features
25 to 400MHz Differential PECL Outputs
±25 ps Peak-to-Peak Output Jitter
Fully Integrated Phase-Locked Loop
Minimal Frequency Over-Shoot
Synthesized Architecture
Serial 3-Wire Interface
Parallel Interface for Power-Up
Quartz Crystal Interface
28-Lead PLCC and 32-Lead LQFP Packages
Operates from 3.3V or 5.0V Power Supply
Functional Description
The internal oscillator uses the external quartz crystal as the basis of its fre-
quency reference. The output of the reference oscillator is divided by 16 before
being sent to the phase detector. With a 16MHz crystal, this provides a refer-
ence frequency of 1MHz. Although this data sheet illustrates functionality only
for a 16MHz crystal, any crystal in the 10–25MHz range can be used.
The VCO within the PLL operates over a range of 200 to 400MHz. Its output is scaled by a divider that is configured by either the
serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output divider
(N divider) is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8).
This divider extends performance of the part while providing a 50 percent duty cycle.
The output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated in
50
to V
CC – 2.0V. The positive reference for the output driver and the internal logic is separated from the power supply for the
phase-locked loop to minimize noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0] inputs
to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the serial
interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs to reduce component count in the application of the
chip.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input. The
serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The configura-
tion latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the programming section
for more information.
The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in the serial data stream. See the pro-
gramming section for more information.
MC12429
FN SUFFIX
28-LEAD PLCC PACKAGE
CASE 776-022
HIGH FREQUENCY PLL
CLOCK SYNTHESIZER
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC12429FN | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:HIGH FREQUENCY PLL CLOCK GENERATOR |
| MC12430FA | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:HIGH FREQUENCY PLL CLOCK GENERATOR |
| MC12430FN | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:HIGH FREQUENCY PLL CLOCK GENERATOR |
| MC12439 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:HIGH FREQUENCY PLL CLOCK GENERATOR |
| MC12439FN | 制造商:Motorola Inc 功能描述: 制造商:Motorola Inc 功能描述:MISCELLANEOUS CLOCK GENERATOR, 28 Pin, Plastic, PLCC |
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