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参数资料
| 型号： | MC12439FNR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 800 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 1/11页 |
| 文件大小： | 128K |
| 代理商： | MC12439FNR2 |
4
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC12439/D
Rev. 6, 09/2001
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
388
High Frequency Clock
Synthesizer
The MC12439 is a general purpose synthesized clock source. Its
internal VCO will operate over a range of frequencies from 400 to 800
MHz. The differential PECL output can be configured to be the VCO
frequency divided by 1, 2, 4, or 8. With the output configured to divide the
VCO frequency by 1, and with a 16.66 MHz external quartz crystal used
to provide the reference frequency, the output frequency can be specified
in 16.66MHz steps. The output frequency is configured using a parallel or
serial interface.
50 to 800 MHz Differential PECL Outputs
±25 ps Typical Peak–to–Peak Output Jitter
Minimal Frequency Over–Shoot
Synthesized Architecture
Serial 3–Wire Interface
Parallel Interface for Power–Up
Quartz Crystal Interface
28–Lead PLCC Package
Operates from 3.3 V or 5.0V Power Supply
Functional Description
The internal oscillator uses the external quartz crystal as the basis of its
frequency reference. The output of the reference oscillator is divided by 2
before being sent to the phase detector. With a 16.66 MHz crystal, this
provides a reference frequency of 8.33 MHz. Although this data sheet
illustrates functionality only for a 16 MHz and 16.66MHz crystal, any
crystal in the 10–20 MHz range can be used. In addition to the crystal, an
LVCMOS input can also be used as the PLL reference. The reference is
selected via the XTAL_SEL input pin.
The VCO within the PLL operates over a range of 400 to 800 MHz. Its output is scaled by a divider that is configured by either
the serial or parallel interfaces. The output of this loop divider is also applied to the phase detector.
The phase detector and loop filter attempt to force the VCO output frequency to be 2 x M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve loop lock.
The output of the VCO is also passed through an output divider before being sent to the PECL output driver. This output
divider is configured through either the serial or the parallel interfaces and can provide one of four division ratios (1, 2, 4, or 8).
This divider extends performance of the part while providing a 50% duty cycle.
The output driver is driven differentially from the output divider and is capable of driving a pair of transmission lines terminated
in 50
to VCC – 2.0 V.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]
inputs to configure the internal counters. Normally, on system reset, the P_LOAD input is held LOW until sometime after power
becomes valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority
over the serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs to reduce component count in the
application of the chip.
The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input. See the pro-
gramming section for more information.
The TEST output reflects various internal node values and is controlled by the T[2:0] bits in the serial data stream. See the
programming section for more information.
The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked by the
PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the
PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
Rev 6
MC12439
HIGH FREQUENCY PLL
CLOCK SYNTHESIZER
FN SUFFIX
28–LEAD PLCC PACKAGE
CASE 776
See Upgrade Product – MPC9239
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