MC13109AFTA PDF资料下载(20/28 页)UNIVERSAL CORDLESS TELEPHONE SUBSYSTEM IC

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参数资料

型号：	MC13109AFTA
厂商：	MOTOROLA INC
元件分类：	无绳电话/电话
英文描述：	UNIVERSAL CORDLESS TELEPHONE SUBSYSTEM IC
中文描述：	TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQFP48
封装：	PLASTIC, LQFP-48
文件页数：	20/28页
文件大小：	1307K
代理商：	MC13109AFTA

MC13109A

MOTOROLA RF/IF DEVICE DATA

“Clk Out” Divider Programming

The “Clk Out” pin is derived from the 2nd local oscillator and

can be used to drive a microprocessor, thereby reducing the

number of crystals required. Figure 19 shows the relationship

between the crystal frequency and the clock output for

different divider values. Figure 20 shows the “Clk Out” register

bit values.

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12.00 MHz

6.000 MHz

4.000 MHz

2.400 MHz

1.200 MHz

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Bit #1

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Bit #2

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Divider Value

MPU “Clk Out” Power–Up Default Divider Value

The power–up default divider value is “divide by 10”. This

provides an MPU clock of about 1.0 MHz after initial

power–up. The reason for choosing this relatively low clock

frequency after intial power–up is that some microprocessors

that operate down to a 2.0 V power supply have a maximum

clock frequency of 1.0 MHz. After initial power–up, the MPU

can change the clock divider value to set the clock to the

desired operating frequency. Special care has been taken in

the design of the clock divider to ensure that the transition

between one clock divider value and another is “smooth”

(i.e., there will be no narrow clock pulses to disturb the MPU).

MPU “Clk Out” Radiated Noise on Circuit Board

The clock line running between the MC13109A and the

microprocessor has the potential to radiate noise which can

cause problems in the system especially if the clock is a

square wave digital signal with large high frequency

harmonics. In order to minimize radiated noise, a 1.0 k

resistor is included on–chip in–series with the “Clk Out” output

driver. A small capacitor can be connected to the “Clk Out” line

on the PCB to form a single pole low pass filter. This filter will

significantly reduce noise radiated from the “Clk Out” line.

Volume Control

The volume control can be programmed in 2.0 dB gain steps

from –14 dB to 16 dB. The power–up default value is 0 dB.

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Gain Control Register

The gain control register contains bits which control the

Carrier Detect threshold. Operation of these latch bits are

explained in Figures 22 and 23.

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Bit #3

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Bit #2

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Bit #1

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Figure 22. Gain Control Latch Bits

Bit #0

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Control #

Amount

–14 dB

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–12 dB

–10 dB

–8.0 dB

–6.0 dB

–4.0 dB

–2.0 dB

0 dB

2.0 dB

4.0 dB

6.0 dB

8.0 dB

10 dB

12 dB

14 dB

16 dB

MSB

LSB

5–Bit CD Threshold Control

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