参数资料
型号: MC13224VR2
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PBGA99
封装: 9.50 X 9.50 MM, 1.20 MM HEIGHT, ROHS COMPLIANT, LGA-99
文件页数: 16/54页
文件大小: 490K
代理商: MC13224VR2
MC1322x Technical Data, Rev. 1.3
Freescale Semiconductor
23
Status flags for various flow control and FIFO states
Receiver detects framing errors, start bit error, break characters, parity errors, and overrun errors.
Voting logic for improved noise immunity (16X/8X oversampling)
Maskable interrupt request
Time-out counter, which times out after eight non-present characters
Receiver and transmitter enable/disable
Low-power modes
Baud rate generator to provide any multiple-of-2 baud rate between 1.2 kbaud and 1,843.2 kbaud
5.5
Inter-Integrated Circuit (I2C) Module
The MC1322x provides an Inter-Integrated Circuit (I2C) module for the I2C which is a two-wire, serial
data (SDA) and serial clock (SCL), bidirectional serial bus. The I2C allows for data exchange between the
MC1322x and other devices such as MCUs, serial EEPROM, serial ADC and DAC devices, and LCDs.
The I2C minimizes interconnections between devices and is a synchronous, multi-master bus that allows
additional devices to be connected and still handle system expansion and development. The bus includes
collision detection and arbitration to prevent data corruption if two or more masters attempt to
simultaneously control the I2C.
The I2C module is driven by the peripheral bus clock (typically 24 MHz) and the SCL bit clock is
generated from a prescaler. The prescaler divide ratio can be programmed from 61,440 to 160 (decimal)
which gives a maximum bit clock of 150 kbps.
The I2C module supports the following features:
Two-wire (SDA and SCL) interface
Multi-master operation
Master or slave mode
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
START and STOP signal generation/detection
Acknowledge bit generation/detection
Bus busy detection
Software-programmable bit clock frequency up to 150 kbps
Software-selectable acknowledge bit
On-chip filtering for spikes on the bus
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