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参数资料
| 型号： | MC13783VKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 26/50页 |
| 文件大小： | 0K |
| 描述： | IC PWR MNGMNT ATLAS 3G 247MAPBGA |
| 标准包装： | 1,500 |
| 应用： | 手持/移动设备 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 247-TFBGA |
| 供应商设备封装： | 247-MAPBGA（10x10） |
| 包装： | 带卷 (TR) |
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Functional Description
4.3
4.3.1
4.3.1.1
Audio
Dual Digital Audio Bus
Interface
The MC13783 is equipped with two independent digital audio busses. Both busses consist of a bit clock,
word clock, receive data and transmit data signal lines. Both busses can be redirected to either the voice
CODEC or the stereo DAC and can be operated simultaneously. In addition to the afore mentioned signal
lines, two system clock inputs are provided which can be selected to drive the voice CODEC or the stereo
DAC. In the latter case, a PLL is used to generate the proper internal frequencies. During simultaneous use
of the both busses, two different system clocks can be selected by the voice CODEC and the stereo DAC.
4.3.1.2
Voice CODEC protocol
The serial interface protocol for the voice CODEC can be used in master and in slave mode. In both modes,
it can operate with a short or a long frame sync and data is transmitted and received in a two's compliment
format.
CDCFS[1:0]=01
Short Frame Sync
Length = Bit
FS
FSync
BitCLK
CDCFS[1:0]=10
Long Frame Sync
Length = 16 Bit
CDCFSINV=0
CDCBCLINV=0
TX
TX
HIGH Z
15 14 13 12 11 10
9
8
7
6
5
4
3
0
0 0
HIGH Z
RX
Don't
Care
15 14 13 12 11 10
9
8
7
6
5
4
3
0
0
0
Don't
Care
Figure 6. Voice Codec Timing Diagram Example 1
When the voice CODEC is in slave mode, the FS input must remain synchronous to the CLI frequency. In
master mode all clocks are internally generated based on the CLI signal.
Additional programmability of the interface for both master and slave mode include bus protocol selection
and FS and BCL inversion. There is also the possibility to activate the clocking circuitry independent from
the voice CODEC.
4.3.1.3
Stereo DAC protocol
The serial interface protocol for the stereo DAC supports the industry standard MSB justified mode and an
I2S mode. In industry standard mode, FS will be held high for one 16-bit data word and low for the next
16 bits. I2S mode is similar to industry standard mode except that the serial data is delayed one BCL
period. Data is received in a two's compliment format. A network mode is also available where the stereo
MC13783 Technical Data, Rev. 3.5
26
Freescale Semiconductor
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