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参数资料
| 型号： | MC13850EPR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 34/54页 |
| 文件大小： | 0K |
| 描述： | IC RF LNA 400MHZ-2.5GHZ 8 MLPD |
| 标准包装： | 1 |
| 频率： | 400MHz ~ 2.5GHz |
| P1dB： | 2.2dBm |
| 增益： | 13dB |
| 噪音数据： | 1.85dB |
| RF 型： | 通用 |
| 电源电压： | 2.3 V ~ 3 V |
| 电流 - 电源： | 9.9mA |
| 测试频率： | 2.4GHz |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | MC13850EPR2DKR |
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Application Information
35
30
25
20
MSG
15
|S21 2 |
MAG
MSG/MAG ? (dB)
|s21|^2 ? (dB)
10
5
0.3
0.8
1.3
1.8
2.3
Frequency ? (GHz)
Figure 13. Maximum Stable/Available Gain and Forward Insertion Gain vs. Frequency (High IP3 Mode)
4
Application Information
The MC13850 LNA is designed for applications in the 400 MHz to 2.5 GHz range. It has four different
modes: Low IP3, High IP3, bypass and standby. The LNA is programmable through the Enable 1 and
Enable 2 pins. In Low IP3 mode, current consumption is optimized. Current consumption is higher in High
IP3 mode to boost the intercept point performance. The gain difference between Low IP3 and High IP3
modes is typically 1.0 dB, and typically the Low and High IP3 modes have similar noise figures. The
internal bypass switch is designed for broadband applications. One of the advantages of the MC13850 is
the simplification of the matching network in both bypass and amplifier modes. The bypass switch is
designed so that changes of input and output return losses between bypass mode and active mode are
minimized. As a result, the mismatch of the LNA input and output is minimized and the matching network
design is simplified.
In the design of the external matching network, conjugate matching does not necessarily provide the best
noise figure and gain performance. Designing for a balance between noise figure, gain, return losses and
intercept point provides circuits that demonstrate overall performance. For a particular application or
specification requirement, the matching can be changed to achieve enhanced performance of one
parameter. Typical circuits are provided for 470 MHz–860 MHz, 900 MHz, 1.96 GHz and 2.4 GHz
applications.
Figure 14 shows the typical application circuit for 470 MHz–860 MHz. The noise figure, input intercept
point, gain and return losses are optimized. L1 and C2 act as a low frequency trap to improve the input
intercept point.
In Figure 15 , the typical application circuit for 900 MHz is shown. The input low frequency trap again is
used to maximize the input intercept point. It has moderate IP3 performance for high gain. Figure 16shows
the 900 MHz application circuit with feedback network for higher IP3. Capacitive feedback is used to
increase the third order input intercept point while decreasing gain and provides unconditional stability.
The corresponding printed circuit boards are shown in Figure 19 through Figure 23 . Table 22 lists the bill
of materials for the application circuit evaluation boards.
MC13850 Advance Information, Rev. 1
34
Freescale Semiconductor
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