参数资料
| 型号： | MC14012BFELG |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/8页 |
| 文件大小： | 0K |
| 描述： | IC GATE NAND DUAL P/N 14SOEIAJ |
| 标准包装： | 2,000 |
| 系列： | 4000B |
| 逻辑类型： | 与非门 |
| 电路数： | 2 |
| 输入数： | 4 |
| 电源电压： | 3 V ~ 18 V |
| 电流 - 静态（最大值）： | 1µA |
| 输出电流高，低： | 8.8mA，8.8mA |
| 逻辑电平 - 低： | 1.5 V ~ 4 V |
| 逻辑电平 - 高： | 3.5 V ~ 11 V |
| 额定电压和最大 CL 时的最大传播延迟： | 100ns @ 15V，50pF |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 供应商设备封装： | SOEIAJ-14 |
| 封装/外壳： | 14-SOIC（0.209"，5.30mm 宽） |
| 包装： | 带卷 (TR) |
MC14012B
http://onsemi.com
6
VOLTAGE TRANSFER CHARACTERISTICS
Figure 11. VDD = 5.0 Vdc
Figure 12. VDD = 10 Vdc
1.0
3.0
5.0
4.0
2.0
0
1.0
3.0
5.0
4.0
2.0
0
Vin, INPUT VOLTAGE (Vdc)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
Figure 13. VDD = 15 Vdc
0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, A
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
12
14
16
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit
values of the input values VIL and VIH for the output(s) to
be at a fixed voltage VO are given in the Electrical
Characteristics table. VIL and VIH are presented graphically
in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Figure 14. DC Noise Immunity
Vout
VO
VIL
0
VIH
Vin
VDD
Vout
VO
VIL
0
VIH
Vin
VDD
(a) Inverting Function
(b) NonInverting Function
VSS = 0 VOLTS DC
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