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参数资料
| 型号： | MC14020BCL |
| 厂商： | MOTOROLA INC |
| 元件分类： | 计数器 |
| 英文描述： | 4000/14000/40000 SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, CDIP16 |
| 封装： | CERAMIC, DIP-16 |
| 文件页数： | 3/6页 |
| 文件大小： | 207K |
| 代理商： | MC14020BCL |
MOTOROLA CMOS LOGIC DATA
89
MC14020B
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Vdc
Min
Typ #
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
—
100
50
40
200
100
80
ns
Propagation Delay Time
Clock to Q1
tPHL, tPLH = (1.7 ns/pF) CL + 175 ns
tPHL, tPLH = (0.66 ns/pF) CL + 82 ns
tPHL, tPLH = (0.5 ns/pF) CL + 55 ns
tPLH,
tPHL
5.0
10
15
—
260
115
80
520
230
160
ns
Clock to Q14
tPHL, tPLH – (1.7 ns/pF) CL + 1735 ns
tPHL, tPLH = (0.66 ns/pF) CL + 772 ns
tPHL, tPLH = (0.5 ns/pF) CL + 535 ns
5.0
10
15
—
1820
805
560
3900
1725
1200
ns
Propagation Delay Time
Reset to Qn
tPHL = (1.7 ns/pF) CL + 285 ns
tPHL = (0.66 ns/pF) CL + 122 ns
tPHL = (0.5 ns/pF) CL + 90 ns
tPHL
5.0
10
15
—
370
155
115
740
310
230
ns
Clock Pulse Width
tWH
5.0
10
15
500
165
125
140
55
38
—
ns
Clock Pulse Frequency
fcl
5.0
10
15
—
2.0
6.0
8.0
1.0
3.0
4.0
MHz
Clock Rise and Fall Time
tTLH, tTHL
5.0
10
15
No Limit
—
Reset Pulse Width
tWL
5.0
10
15
3000
550
420
320
120
80
—
ns
Reset Removal Time
trem
5.0
10
15
130
50
30
65
25
15
—
ns
* The formulas given are for the typical characteristics only at 25
_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Power Dissipation Test Circuit
and Waveform
Figure 2. Switching Time Test Circuit
and Waveforms
500
F
0.01
F
CERAMIC
PULSE
GENERATOR
VDD
CL
VSS
C
R
Q1
Q4
Qn
ID
VDD
VSS
20 ns
CLOCK
90%
50%
10%
50% DUTY CYCLE
PULSE
GENERATOR
VDD
VSS
C
R
Q1
Q4
Qn
CL
20 ns
CLOCK
90%
50%
10%
tWH
tPLH
tPHL
90%
50%
10%
tTLH
tTHL
Q
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