参数资料
型号: MC14025BCPG
厂商: ON Semiconductor
文件页数: 6/12页
文件大小: 0K
描述: IC GATE NOR TRIPLE CMOS 14DIP
标准包装: 25
系列: 4000B
逻辑类型: 或非门
电路数: 3
输入数: 3
电源电压: 3 V ~ 18 V
电流 - 静态(最大值): 1µA
输出电流高,低: 8.8mA,8.8mA
逻辑电平 - 低: 1.5 V ~ 4 V
逻辑电平 - 高: 3.5 V ~ 11 V
额定电压和最大 CL 时的最大传播延迟: 100ns @ 15V,50pF
工作温度: -55°C ~ 125°C
安装类型: 通孔
供应商设备封装: 14-PDIP
封装/外壳: 14-DIP(0.300",7.62mm)
包装: 管件
产品目录页面: 1124 (CN2011-ZH PDF)
其它名称: MC14025BCPGOS
MC14001B Series
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
55_C
25_C
125_C
Unit
Min
Max
Min
Typ (2)
Max
Min
Max
Output Voltage
“0” Level
Vin = VDD or 0
VOL
5.0
10
15
0.05
0
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD
VOH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vdc
Output Drive Current
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
– 1.7
– 0.36
– 0.9
– 2.4
mAdc
(VOL = 0.4 Vdc)
Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current
Iin
15
± 0.1
±0.00001
± 0.1
± 1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
5.0
7.5
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
mAdc
Total Supply Current (3) (4)
(Dynamic plus Quiescent,
Per Gate, CL = 50 pF)
IT
5.0
10
15
IT = (0.3 mA/kHz) f + IDD/N
IT = (0.6 mA/kHz) f + IDD/N
IT = (0.9 mA/kHz) f + IDD/N
mAdc
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates
per package.
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