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参数资料
| 型号： | MC14049BCL |
| 厂商： | MOTOROLA INC |
| 元件分类： | 门电路 |
| 英文描述： | 4000/14000/40000 SERIES, HEX 1-INPUT INVERT GATE, CDIP16 |
| 封装： | CERAMIC, DIP-16 |
| 文件页数： | 2/6页 |
| 文件大小： | 203K |
| 代理商： | MC14049BCL |
MOTOROLA CMOS LOGIC DATA
MC14049B MC14050B
2
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
– 55
_C
+ 25
_C
+ 125
_C
Unit
Characteristic
Symbol
VDD
Vdc
Min
Max
Min
Typ1
Max
Min
Max
Unit
Output Voltage
“0” Level
Vin = VDD
“1” Level
Vin = 0
VOL
5.0
10
15
—
0.05
—
0
0.05
—
0.05
Vdc
“1” Level
Vin = 0
VOH
5.0
10
15
4.95
9.95
14.95
—
4.95
9.95
14.95
5.0
10
15
—
4.95
9.95
14.95
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
“1” Level
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
VIL
5.0
10
15
—
1.5
3.0
4.0
—
2.25
4.50
6.75
1.5
3.0
4.0
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
—
3.5
7.0
11
2.75
5.50
8.25
—
3.5
7.0
11
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc)
Source
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH
5.0
10
15
– 1.6
– 4.7
—
– 1.25
– 1.30
– 3.75
– 2.5
– 2.6
– 10
—
– 1.0
– 3.0
—
mAdc
(VOL = 0.4 Vdc)
Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL
5.0
10
15
3.75
10
30
—
3.2
8.0
24
6.0
16
40
—
2.6
6.6
19
—
mAdc
Input Current
Iin
15
—
± 0.1
—
±0.00001
± 0.1
—
± 1.0
Adc
Input Capacitance (Vin = 0)
Cin
—
—
—
—
10
20
—
—
pF
Quiescent Current (Per Package)
IDD
5.0
10
15
—
1.0
2.0
4.0
—
0.002
0.004
0.006
1.0
2.0
4.0
—
30
60
120
Adc
Total Supply Current 2,3
(Dynamic plus Quiescent,
per package)
(CL = 50 pF on all outputs, all
buffers switching
IT
5.0
10
15
IT = (1.8 A/kHz) f + IDD
IT = (3.5 A/kHz) f + IDD
IT = (5.3 A/kHz) f + IDD
Adc
1 Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
2 The formulas given are for the typical characteristics only at + 25_C
3 To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
Where:
IT is in A (per Package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency and k = 0.002.
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields
referenced to the VSS pin only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum
rated voltages to this high-impedance circuit. For proper operation, the ranges VSS v Vin v 18 V and VSS v Vout v VDD are
recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be
left open.
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