参数资料
型号: MC14081BD
厂商: MOTOROLA INC
元件分类: 门电路
英文描述: 4000/14000/40000 SERIES, QUAD 2-INPUT AND GATE, PDSO14
封装: PLASTIC, SOIC-14
文件页数: 11/11页
文件大小: 327K
代理商: MC14081BD
MOTOROLA CMOS LOGIC DATA
15
MC14001B
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d)
VOLTAGE TRANSFER CHARACTERISTICS
Figure 8. VDD = 5.0 Vdc
Figure 9. VDD = 10 Vdc
1.0
3.0
5.0
4.0
2.0
0
1.0
3.0
5.0
4.0
2.0
0
Vin, INPUT VOLTAGE (Vdc)
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
Figure 10. VDD = 15 Vdc
0
SINGLE INPUT NAND, AND
MULTIPLE INPUT NOR, OR
SINGLE INPUT NOR, OR
MULTIPLE INPUT NAND, AND
2.0
6.0
10
8.0
4.0
2.0
6.0
10
8.0
4.0
Vin, INPUT VOLTAGE (Vdc)
12
14
16
V
,
out
OUTPUT
VOL
TAGE
(Vdc)
DC NOISE MARGIN
The DC noise margin is defined as the input voltage range
from an ideal “1” or “0” input level which does not produce
output state change(s). The typical and guaranteed limit val-
ues of the input values VIL and VIH for the output(s) to be at a
fixed voltage VO are given in the Electrical Characteristics
table. VIL and VIH are presented graphically in Figure 11.
Guaranteed minimum noise margins for both the “1” and
“0” levels =
1.0 V with a 5.0 V supply
2.0 V with a 10.0 V supply
2.5 V with a 15.0 V supply
Figure 11. DC Noise Immunity
Vout
VO
VIL
0
VIH
Vin
VDD
Vout
VO
VIL
0
VIH
Vin
VDD
(a) Inverting Function
(b) Non–Inverting Function
VSS = 0 VOLTS DC
相关PDF资料
PDF描述
MC14001BCP 4000/14000/40000 SERIES, QUAD 2-INPUT NOR GATE, PDIP14
MC14081BCP 4000/14000/40000 SERIES, QUAD 2-INPUT AND GATE, PDIP14
MC14012BCP 4000/14000/40000 SERIES, DUAL 4-INPUT NAND GATE, PDIP14
MC14073BCP 4000/14000/40000 SERIES, TRIPLE 3-INPUT AND GATE, PDIP14
MC14081BF 4000/14000/40000 SERIES, QUAD 2-INPUT AND GATE, PDSO14
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