参数资料
型号: MC145011DW
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 模拟信号调理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO16
封装: PLASTIC, SOIC-16
文件页数: 2/12页
文件大小: 346K
代理商: MC145011DW
Sensors
10
Freescale Semiconductor
MC145011
CALIBRATION
To facilitate checking the sensitivity and calibrating smoke
detectors, the MC145011 can be placed in a calibration
mode. In this mode, certain device pins are controlled/
reconfigured as shown in Table 5. To place the part in the
calibration mode, Pin 16 (Test) must be pulled below the VSS
pin with 100
A continuously drawn out of the pin for at least
one cycle on the OSC pin. To exit this mode, the Test pin is
floated for at least one OSC cycle.
In the calibration mode, the IRED pulse rate is increased
to one for every OSC cycle. Also, Strobe is always active low.
Figure 9. Recommended PCB Layout
Table 5. Configuration of Pins in the Calibration Mode
Pin
Description
Comment
7
I/O
Disabled as an output. Forcing this pin high places the photo amp output on pin 1 or 2, as determined
by Low-Supply Trip. The amp's output appears as pulses and is referenced to VDD.
15
Low-Supply Trip
If the I/O pin is high, pin 15 controls which gain capacitor is used. Low: normal gain, amp output on
pin 1. High: supervisory gain, amp output on pin 2.
10
Feedback
Driving this input high enables hysteresis (10% gain increase) in the photo amp; pin 15 must be low.
12
Osc
Driving this input high brings the internal clock high. Driving the input low brings the internal clock low.
If desired, the RC network for the oscillator may be left intact; this allows the oscillator to run similar to
the normal mode of operation.
9
Silver
This pin becomes the smoke comparator output. When the OSC pin is toggling, positive pulses indicate
that smoke has been detected. A static low level indicates no smoke.
8
Brass
This pin becomes the smoke integrator output. That is, 2 consecutive smoke detections are required
for “on” (static high level) and 2 consecutive no-detections for “off” (static low level).
NOTES: Illustration is bottom view of layout using a DIP. Top view for SOIC layout is mirror image.
Optional potentiometer R9 is not included.
Drawing is not to scale.
Leads on D1, R11, R8, and R10 and their associated traces must be kept as short as possible.
This practice minimizes noise pick up.
Pin 3 must be decoupled from all other traces.
Pin 8
Pin 16
Pin 9
Pin 1
C1
R11
D2
R8
MOUNTED IN
CHAMBER
C2
R1
0
Do Not Run Any
Additional Traces
In This Region
C2
R14
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