参数资料
型号: MC14532BFR2
厂商: ON SEMICONDUCTOR
元件分类: 算术逻辑单元
英文描述: 4000/14000/40000 SERIES, 8-BIT ENCODER, PDSO16
封装: EIAJ, SO-16
文件页数: 4/7页
文件大小: 95K
代理商: MC14532BFR2
MC14532B
http://onsemi.com
320
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Min
Typ (8.)
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time — Ein to Eout
tPLH, tPHL = (1.7 ns/pF) CL + 120 ns
tPLH, tPHL = (0.66 ns/pF) CL + 77 ns
tPLH, tPHL = (0.5 ns/pF) CL + 55 ns
tPLH,
tPHL
5.0
10
15
205
110
80
410
220
160
ns
Propagation Delay Time — Ein to GS
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns
tPLH, tPHL = (0.66 ns/pF) CL 57 ns
tPLH, tPHL = (0.5 ns/pF) CL + 40 ns
tPLH,
tPHL
5.0
10
15
175
90
65
350
180
130
ns
Propagation Delay Time — Ein to Qn
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns
tPLH, tPHL = (0.66 ns/pF) CL + 107 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPHL,
tPLH
5.0
10
15
280
140
100
560
280
200
ns
Propagation Delay Time — Dn to Qn
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns
tPLH, tPHL = (0.66 ns/pF) CL + 137 ns
tPLH, tPHL = (0.5 ns/pF) CL + 85 ns
tPLH,
tPHL
5.0
10
15
300
170
110
600
340
220
ns
Propagation Delay Time — Dn to GS
tPLH, tPHL = (1.7 ns/pF) CL + 195 ns
tPLH, tPHL = (0.66 ns/pF) CL + 107 ns
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns
tPLH,
tPHL
5.0
10
15
280
140
100
560
280
200
ns
7. The formulas given are for the typical characteristics only at 25
_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Output
Under
VGS = VDD
VDS = Vout
Sink Current
VGS = – VDD
VDS = Vout – VDD
Source Current
Under
Test
D0 thru D7
Ein
D0 thru D6
D7
Ein
Eout
X
0
1
Eout
Q0
X
0
1
Q0
Q1
Q2
X
0
1
Q2
GS
X
0
1
GS
X
0
1
Figure 1. Typical Sink and Source
Current Characteristics
Figure 2. Typical Power Dissipation Test Circuit
SWITCH
MATRIX
EXTERNAL
POWER
SUPPLY
ID
Ein
D0
D1
D2
D3
D4
D5
D6
D7
GS
Q2
Q1
Q0
Eout
Vout
PULSE
GENERATOR
(fo)
Ein
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
ID
CL
GS
Q2
Q1
Q0
Eout
0.01
F
500
F
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