参数资料
型号: MC14536BDWG
厂商: ON Semiconductor
文件页数: 13/14页
文件大小: 0K
描述: IC OSC PROG TIMER 2MHZ 16SOIC
标准包装: 47
类型: 可编程计时器
频率: 2MHz
电源电压: 3 V ~ 18 V
电流 - 电源: 15µA
工作温度: -55°C ~ 125°C
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
包装: 管件
供应商设备封装: 16-SOIC W
安装类型: 表面贴装
产品目录页面: 1125 (CN2011-ZH PDF)
其它名称: MC14536BDWG-ND
MC14536BDWGOS
MC14536B
http://onsemi.com
8
Figure 8. Power Dissipation Test
Circuit and Waveform
Figure 9. Switching Time Test Circuit and Waveforms
VDD
0.01
mF
CERAMIC
500
mF
ID
CL
VSS
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
20 ns
90%
10%
50%
DUTY CYCLE
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
CL
VSS
VDD
20 ns
50%
IN1
tWL
tWH
50%
tPHL
90%
10%
tPLH
tTLH
tTHL
OUT
FUNCTIONAL TEST SEQUENCE
Test function (Figure 10) has been included for the
reduction of test time required to exercise all 24 counter
stages. This test function divides the counter into three
8stage sections and 255 counts are loaded in each of the
8stage sections in parallel. All flipflops are now at a “1”.
The counter is now returned to the normal 24stages in
series configuration. One more pulse is entered into In1
which will cause the counter to ripple from an all “1” state
to an all “0” state.
Figure 10. Functional
Test Circuit
VDD
VSS
PULSE
GENERATOR
SET
RESET
8-BYPASS
IN1
C INH
MONO-IN
OSC INH
C
B
A
D
OUT 1
OUT
2
DECODE
OUT
FUNCTIONAL TEST SEQUENCE
Inputs
Outputs
Comments
In1
Set
Reset
8Bypass
Decade Out
Q1 thru Q24
All 24 stages are in Reset mode.
1
0
1
0
1
0
Counter is in three 8 stage sections in parallel mode.
0
1
0
First “1” to “0” transition of clock.
1
0
1
255 “1” to “0” transitions are clocked in the counter.
0
1
The 255 “1” to “0” transition.
0
1
Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1
0
1
In1 Switches to a “1”.
0
Counter Ripples from an all “1” state to an all “0” state.
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