参数资料
| 型号： | MC145423DT |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 13/15页 |
| 文件大小： | 0K |
| 描述： | IC TXRX UDLT/ISDN 28TSSOP |
| 标准包装： | 50 |
| 类型： | 收发器 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
MC145423
TELECOMMUNICATIONS
16
23
RE2/
BCLK
Output
BCLK =
128 kHz
BCLK = 0
BCLK =
128 kHz
BCLK =
128 kHz
BCLK =
128 kHz
BCLK =
128 kHz
24
Rx
Input
64 kbps
Data In
Don’t Care
25
LO2
Output
Modulator
Out
Modulator
Out
LO2 = LO1
26
LO1
Output
Modulator
Out
Modulator
Out
LO1 = LO2
27
MASTER/
SLAVE
Input
111111
28
VDD
Power
+V
+V+V+V+V
MC145423 UDLT-3 PIN STATES FOR UDLT-1 SLAVE MODE (continued)
MC145423
UDLT-1 Slave Mode
Powered-Up
UDLT-1 Slave Mode Powered-Down
TONE = 0, Off
TONE = 1, On
Pin
No.
Pin
Name
In/out
Normal
LB Low
No Valid
Burst Rec’d
Valid
Burst Rec’d
No Valid
Burst Rec’d
Valid
Burst Rec’d
MC145423 UDLT-3 PIN STATES FOR UDLT-1 MASTER MODE
MC145423
UDLT-1 Master Mode
Powered-Up
UDLT-1 Master Mode
Powered-Down
Pin
No.
Pin
Name
In/out
Normal
LB Low
SE Low
Normal
SE Low
1VSS
Power
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
Power Supply
Gnd
2Vref
Analog
Ref
AGND VDD/2
3
LI
Input
Analog In
Don’t Care
Analog In
4LB
Input
1
0
State Latched
Don’t Care
5
VD
Output
Digital out
High Impedance
Digital out
High Impedance
6
SDI1
Input
8 kbps Data In
State Latched
8 kbps Data In
State Latched
7
SDI2
Input
8 kbps Data In
State Latched
8 kbps Data In
State Latched
8
FRAME 10/20
Input
00000
9
SDCLK
Don’t Care High Impedance High Impedance High Impedance High Impedance High Impedance
10
SDO1
Output
8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance
11
SDO2
Output
8 kbps Data Out 8 kbps Data Out High Impedance 8 kbps Data Out High Impedance
12
SE/(Mu/A)
Input
11010
13
PD
Input
1
State Latched
0
State Latched
14
MOD
TRI/SQ
Input
00000
15
Tx
Output
64 kbps
Data Out
64 kbps
Data Out
64 kbps
Data Out
64 kbps
Data Out
64 kbps
Data Out
16
EN2-TE2/
SIE/B1B2
Input
SIE Digital In
TELECOMMUNICATIONS
13
MC145423
SE
SDO1, SDO2, VD
th
Figure 6. SE Pin Timing
tdly1
tsu
tdly2
PREVIOUS STATE
INTERNALLY LATCHED
LB, PD
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For More Information On This Product,
Go to: www.freescale.com
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