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参数资料
| 型号： | MC14553BCP |
| 厂商： | MOTOROLA INC |
| 元件分类： | 计数器 |
| 英文描述： | 4000/14000/40000 SERIES, SYN NEGATIVE EDGE TRIGGERED 12-BIT UP DECADE COUNTER, PDIP16 |
| 封装： | PLASTIC, DIP-16 |
| 文件页数： | 5/8页 |
| 文件大小： | 231K |
| 代理商： | MC14553BCP |
MOTOROLA CMOS LOGIC DATA
5
MC14553B
OPERATING CHARACTERISTICS
The MC14553B three–digit counter, shown in Figure 3,
consists of three negative edge–triggered BCD counters
which are cascaded in a synchronous fashion. A quad latch
at the output of each of the three BCD counters permits stor-
age of any given count. The three sets of BCD outputs
(active high), after going through the latches, are time divi-
sion multiplexed, providing one BCD number or digit at a
time. Digit select outputs (active low) are provided for display
control. All outputs are TTL compatible.
An on–chip oscillator provides the low frequency scanning
clock which drives the multiplexer output selector. The fre-
quency of the oscillator can be controlled externally by a
capacitor between pins 3 and 4, or it can be overridden and
driven with an external clock at pin 4. Multiple devices can be
cascaded using the overflow output, which provides one
pulse for every 1000 counts.
The Master Reset input, when taken high, initializes the
three BCD counters and the multiplexer scanning circuit.
While Master Reset is high the digit scanner is set to digit
one; but all three digit select outputs are disabled to prolong
display life, and the scan oscillator is inhibited. The Disable
input, when high, prevents the input clock from reaching the
counters, while still retaining the last count. A pulse shaping
circuit at the clock input permits the counters to continue op-
erating on input pulses with very slow rise times. Information
present in the counters when the latch input goes high, will
be stored in the latches and will be retained while the latch
input is high, independent of other inputs. Information can be
recovered from the latches after the counters have been re-
set if Latch Enable remains high during the entire reset cycle.
Figure 3. Expanded Block Diagram
PULSE
SHAPER
CLOCK
12
11
DISABLE
(ACTIVE
HIGH)
C
R
Q0
Q1
Q2
Q3
÷10
UNITS
C
R
Q0
Q1
Q2
Q3
÷10
TENS
C
R
Q0
Q1
Q2
Q3
÷10
HUNDREDS
10
LATCH ENABLE
QUAD
LATCH
QUAD
LATCH
QUAD
LATCH
R
SCAN
OSCILLATOR
SCANNER
PULSE
GENERATOR
C1
4
3
C1A
C1B
MULTIPLEXER
9
7
6
5
Q0
Q1
Q2
Q3
BCD
OUTPUTS
(ACTIVE
HIGH)
13
14
2
1
15
MR
(ACTIVE HIGH)
OVERFLOW
DS1
DS2
DS3
(LSD) DIGIT SELECT (MSD)
(ACTIVE LOW)
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| MC14554BCPDS | 4000/14000/40000 SERIES, 2-BIT MULTIPLIER, PDIP16 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC14553BCPG | 功能描述:计数器移位寄存器 3-18V 3-Digit BCD RoHS:否 制造商:Texas Instruments 计数器类型: 计数顺序:Serial to Serial/Parallel 电路数量:1 封装 / 箱体:SOIC-20 Wide 逻辑系列: 逻辑类型: 输入线路数量:1 输出类型:Open Drain 传播延迟时间:650 ns 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装:Reel |
| MC14553BCPG | 制造商:ON Semiconductor 功能描述:Counter / Multiplier / Divider Logic IC |
| MC14553BDW | 制造商:ON Semiconductor 功能描述:Counter Triple 3-Bit Decade UP 16-Pin SOIC Rail |
| MC145554DW | 制造商:Rochester Electronics LLC 功能描述:PCM CODEC-FILTER - Bulk |
| MC145554DWR2 | 制造商:Rochester Electronics LLC 功能描述:MONOCIRCUIT - Bulk |
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