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参数资料
| 型号： | MC1496P1G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/14页 |
| 文件大小： | 0K |
| 描述： | IC MODULATOR/DEMODULATOR 14-DIP |
| 标准包装： | 500 |
| 功能： | 调制器/解调器 |
| 频率： | 300MHz |
| RF 型： | FM |
| 封装/外壳： | 14-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
MC1496, MC1496B
? Vo + 0
g 21C +
Bias currents flowing into Pins 1, 4, 8 and 10 are transistor
base currents and can normally be neglected if external bias
dividers are designed to carry 1.0 mA or more.
Transadmittance Bandwidth
Carrier transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
i o (each sideband)
v s (signal)
Signal transadmittance bandwidth is the 3.0 dB bandwidth
of the device forward transadmittance as defined by:
Negative Supply
V EE should be dc only. The insertion of an RF choke in
series with V EE can enhance the stability of the internal
current sources.
Signal Port Stability
Under certain values of driving source impedance,
oscillation may occur. In this event, an RC suppression
network should be connected directly to each input using
short leads. This will reduce the Q of the source ? tuned
circuits that cause the oscillation.
g 21S + v (signal)
i o (signal)
s
? Vc + 0.5 Vdc, Vo + 0
Signal Input
(Pins 1 and 4)
510
10 pF
Coupling and Bypass Capacitors
Capacitors C1 and C2 (Figure 5) should be selected for a
reactance of less than 5.0 W at the carrier frequency.
Output Signal
The output signal is taken from Pins 6 and 12 either
balanced or single ? ended. Figure 11 shows the output levels
of each of the two output sidebands resulting from variations
An alternate method for low ? frequency applications is to
insert a 1.0 k W resistor in series with the input (Pins 1, 4). In
this case input current drift may cause serious degradation
of carrier suppression.
in both the carrier and modulating signal inputs with a
single ? ended output connection.
TEST CIRCUITS
1.0 k
1.0 k
V CC
12 Vdc
R e = 1.0 k
Carrier
Input
V C
V S
Modulating
C 2
0.1 m F
51
C1
0.1 m F
8
10
1
4
2
R e
1.0 k
MC1496
3
R L
3.9 k
6
12
I9 I6
R L
3.9 k
+V o
? V o
Z in
0.5 V 8
+ ? 10
1
4
2
MC1496
14
3
5
6
12
+V o
Z out
? V o
Signal Input
10 k
10 k 51
51
14
5
6.8 k
R1
50 k
Carrier Null
I10
V ?
?8.0 Vdc
V EE
I5
6.8 k
NOTE:
?8.0 Vdc
Shielding of input and output leads may be needed
to properly perform these tests.
Figure 5. Carrier Rejection and Suppression
Figure 6. Input ? Output Impedance
V CC
12 Vdc
1.0 k
1.0 k
V CC
12 Vdc
1.0 k
1.0 k
I7
I8
I1
I4
8
10
1
4
2
R e = 1.0 k
MC1496
14
3
5
6
12
I6
I9
2.0 k
Carrier
Input 0.1 m F
V C
V S
Modulating
Signal Input
10 k
51
10 k
0.1 m F
51
8
10
1
4
51
2
R e
1.0 k
MC1496
14
3
5
6
12
2.0 k
50 50
0.01
m F
+V o
? V o
I10
?8.0 Vdc
6.8 k
50 k
Carrier Null
V ?
?8.0 Vdc
6.8 k
V EE
Figure 7. Bias and Offset Currents
V EE
Figure 8. Transconductance Bandwidth
http://onsemi.com
5
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