参数资料
型号: MC2800
厂商: Motorola, Inc.
英文描述: FSK FM IF Receiver(FSK FM IF 接收器)
中文描述: FSK信号调频(FSK信号调频中频接收器中频接收机)
文件页数: 6/28页
文件大小: 473K
代理商: MC2800
MC2800
6
MOTOROLA RF/IF DEVICE DATA
BD Out WITH 100 k
(LOW BATTERY DETECTOR)
BD Out
H
Low Battery
L
D1 WITH 100 k
(D1)
D1
H
Dev –4.8 kHz or Dev –1.6 kHz
L
Dev 1.6 kHz or Dev 4.8 kHz
D2 WITH 100 k
(D2)
D2
H
Dev
±
1.6 kHz
L
Dev
±
4.8 kHz
FUNCTIONAL DESCRIPTION
The complete circuit consists of the following functional
blocks as shown in the Block Diagram on page 1.
Oscillator
The oscillator is based on a transistor in common collector
configuration. It requires two external capacitors and a
crystal to form the tank circuit. External capacitors between
base and emitter and from emitter to RF Pwr make the
oscillator transistor to have a negative resistance for small
signals which is the start–up condition for oscillation.
Mixer
The mixer consists of input v–to–i stage and upper
switching stage driven from the oscillator. The LO drive is fed
from the built–in oscillator. The mixer output is obtained at
Mix Out.
IF Amplifier and Limiter
The first ceramic filter is to obtain the 455 kHz IF and to
remove all other harmonics from the mixing process. The
mixer output signal is then amplified in the first IF Amplifier.
The signal is then fed into the second IF Amplifier through the
second ceramic filter. The final IF signal can be monitored at
the limiter output pin Lim Op.
RSSI function
The RSSI function is an indication of the strength of the
incoming signal.
Demodulator
The limiter output @ 455 kHz is fed into the gyrator for
carrier recovery and 90
°
phase shift. This LO signal is then
mixed with the FSK signal fed by the IF Amp for
demodulation. The demodulator output can be obtained at
Det Out.
Bit–Rate Filter
The cut–off frequencies of the filter can be determined by
the 2.2 nF external capacitor between Pins BRF Out and
BRF1, and the 22 nF external capacitor at Pin BRF2. The
filter bandwidth can be switched by Pins R1 and R2 for both
POCSAG and FLEX requirements.
A/D Convertor
The A/D converter features a fully adaptive data slicer. The
input to the converter at Pin BRF Out is initially
peak–detected. Its peak and valley voltages are obtained at
Pins VPk P and VPk N. Three threshold voltages at 1/6, 1/2
and 5/6 of the input signal level are determined dynamically
regardless the actual peak–to–peak value. The final digital
data are obtained at Pins D1 and D2 depending upon the 2 or
4 levels FSK signal.
Low Battery Detector
The battery low indicator senses the supply voltage and
sets its output High when the voltage at input VCC is less than
Vth (typically 1.1 V).
Band Gap Reference
The whole chip can be powered–up and powered–down
by enabling and disabling the band gap reference via the Pin
EN (Enable).
1.0 V Regulator
The 1.0 V voltage at Pin Vreg is used to supply the
regulated voltage for the oscillator and the mixer. It can also
be used to supply other external circuits.
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