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参数资料
| 型号： | MC33143 |
| 厂商： | 飞思卡尔半导体(中国)有限公司 |
| 英文描述： | DUAL HIGH–SIDE SWITCH(双高端开关) |
| 中文描述： | 双高边开关（双高端开关） |
| 文件页数： | 4/8页 |
| 文件大小： | 279K |
| 代理商： | MC33143 |
MC33143
4
MOTOROLA ANALOG IC DEVICE DATA
DC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions 9.0 V
≤
VPwr
≤
17 V, 4.5 V
≤
VDD 5.5 V,
–40
°
C
≤
TL
≤
125
°
C, unless otherwise noted, typical values represent approximate mean at TL = 25
°
C.)
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL INTERFACE
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Logic High (IO = –0.1 A) (Note 1)
Logic Low (IO = 0) (Note 2)
Input Logic Voltage Hysteresis (VIH – VIL)
Input Pull–Down Current (0.3 x VDD
≤
Vin < 0.7 x VDD) (Note 3)
Chip–Enable Threshold
Logic Low (Note 4)
Input Control
VIH
VIL
Vhys
Iin(pd)
0.7
–
–
0.56
0.52
0.5
–
0.3
0.3
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VCEN(IL)
VCEN(hys)
VSTAT(low)
50
250
500
mV
20
44
100
μ
A
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Logic Low
INTl
–
–
0.3
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Logic High
–2.0
–16.8
–40
μ
A
0.7
–
–
NOTES:
1.Upper logic threshold voltage applies to IN1, IN2, and SFPD and expressed in VDD units
2.Lower logic threshold voltage applies to IN1, IN2, and SFPD and expressed in VDD units.
3.Applies to IN1, IN2, and SFPD.
4.Initially have CEN = 0.7 x VDD, Ramp CEN down from VDD until IO = 0 and note disabling point.
5.Initially have Vin = 0.7 x VDD, Ramp CEN up from ground until IO = 0.1 A and note enabling point.
6.Applies equally to STAT1–2 and INT outputs; Measured threshold voltage by applying an “open” fault to OUT1 or OUT2 while forcing 600
μ
A of
current into STAT1–2 or INT.
7.Measured with no faults on OUT1–2, VSTAT = VINT = 0.8 x VDD.
8. The Interrupt output has an internal active current pull–up
.
DC ELECTRICAL CHARACTERISTICS
(Characteristics noted under conditions 9.0 V
≤
VPwr
≤
17 V, 4.5 V
≤
VDD 5.5 V,
–40
°
C
≤
TL
≤
125
°
C, unless otherwise noted, typical values represent approximate mean at TL = 25
°
C.)
Characteristic
Symbol
Min
Typ
Max
Unit
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Turn–Off (Output High to Low) (Note 5)
tdhl
–
40
75
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Output Falling (Note 7)
Output Slew Rate
SRr
SRf
0.2
0.2
11
2.6
10
10
V/
μ
s
NOTES:
1.CEN = 0.7 x VDD, SFPD = 0.3 x VDD, RL = 0, Step Vin from 0.3 x VDD to 0.7 x VDD; Sense time measured from step until STAT = 0.2 x VDD.
2.CEN = IN1 = IN2 = 0.7 x VDD, RL = 0; Refresh time measured from output disable until output is re–enabled.
3.RL = “open”, Step Vin from ground to 0.7 x VDD, Open sense time measured from step until VSTAT
≤
0.2 x VDD.
4.RL = 12
, CL = 0.01
μ
F, step Vin from VIL to VIH; Turn–On propagation measured from Vin = 0.5 x VDD until Vout = 2.0 V (see Figure 2).
5.RL = 12
, CL = 0.01
μ
F, step Vin from VIH to VIL; Turn–Off propagation measured from Vout = VPwr –3.0 V until Vout = 2.0 V (see Figure 2).
6.RL = 12
, CL = 0.01
μ
F, step Vin from VIL to VIH; Output Slew Rate measured from 2.0 V to VPwr – 3.0 V (see Figure 2).
7.RL = 12
, CL = 0.01
μ
F, step Vin from VIH to VIL; Output Slew Rate measured from VPwr – 3.0 V to 2.0 V (see Figure 2).
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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