参数资料
型号: MC33364D2G
厂商: ON Semiconductor
文件页数: 11/16页
文件大小: 0K
描述: IC CTRLR SMPS OTP UVLO 8SOIC
标准包装: 98
系列: GreenLine™
输出隔离: 隔离
频率范围: 104kHz ~ 800kHz
输入电压: 8.5 V ~ 16 V
输出电压: 700V
工作温度: -25°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 管件
其它名称: MC33364D2GOS
MC33364
? V sat
5.0 V ? 0.3 V
= ref
collector
I
5.0 mA
(5.0 k)(940)
int
collector
R ext = R3 = (R =
V out
noload
(I
+ I
)
= 1143 Ω
(5.0 mA + 0.25 mA)
f ph =
? Vin max ? Vout ? Ns ? 382 V ? 6.0 V ? 2(7)
? (Vin max)(Verror)(Np) ? (382 V)(1.2 V)(139)
f c = fs min =
= 14 kHz
? ? ? 14 kHz ? ? 23.82 dB
fc
Gc = 20 log ? A = 20 log
ph
= R upper || R
in
lower
= 0.46 Hz
=
= 382 pF ≈ 390 pF
C8 =
The MOC8102 has a typical current transfer ratio (CTR)
of 100% with 25% tolerance. When the TL431 is full--on,
5 mA will be drawn from the transistor within the
MOC8102. The transistor should be in saturated state at that
time, so its collector resistor must be
V
R = = 940 Ω
LED
Since a resistor of 5.0 k is internally connected from the
reference voltage to the feedback pin of the MC33364, the
external resistor can have a higher value
(R )(R )
int ) ? (R collector ) 5.0 k ? 940
= 1157 Ω ≈ 1200 Ω
This completes the design of the voltage feedback circuit.
In no load condition there is only a current flowing
through the optoisolator diode and the voltage sense divider
on the secondary side.
The load at that condition is given by:
R =
LED div
6.0 V
=
The output filter pole at no load is:
1
( 2 π R noload C out )
1
(2 π )(1143)(300 m F)
In heavy load condition the I LED and I div is negligible. The
heavy load resistance is given by:
The gain exhibited by the open loop power supply at the
high input voltage will be:
2
A = =
= 15.53 = 23.82 dB
The maximum recommended bandwidth is
approximately:
70 kHz
5 5
The gain needed by the error amplifier to achieve this
bandwidth is calculated at the rated load because that yields
the bandwidth condition, which is:
f
= 14.14 dB
The gain in absolute terms is:
A c = 10 (Gc ∕ 20) = 10 (14.14 ∕ 20) = 5.1
Now the compensation circuit elements can be calculated.
The output resistance of the voltage sense divider is given by
the parallel combination of resistors in the divider:
R = 10 k || 14 k = 5833 Ω
R9 = (Ac) (R in ) = 29.75 k ≈ 30 k
1
? 2 π (Ac) (Rin) (fc) ?
The compensation zero must be placed at or below the
= out =
heavy
I out
2.0 A
C7 =
V 6.0 V
R = 3.0 Ω
The output filter pole at heavy load of this output is
light load filter pole:
1
? 2 π (R9) (fpn) ?
= 11.63 m F ≈ 10 m F
f ph =
1
(2 π R heavyC out)
=
1
(2 π )(3)(300 m F)
= 177 Hz
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