参数资料
| 型号： | MC33470DW |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/15页 |
| 文件大小： | 0K |
| 描述： | IC CONV DC/DC SYNC RECT 20-SOIC |
| 产品变化通告： | Product Obsolescence 11/Feb/2009 |
| 标准包装： | 38 |
| 应用： | 控制器，Intel Pentium? II |
| 输入电压： | 4.5 V ~ 5.5 V |
| 输出数： | 1 |
| 输出电压： | 1.8 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 管件 |
ELECTRICAL CHARACTERISTICS (V CC = 5.0 V, P P V VCC , = 12 V for typical values T A = Low to High [Notes 2, 3, 4], for
MC33470
CC
min/max values T A is the operating ambient temperature range that applies, unl ess otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Frequency (V CC = 4.5 to 5.5 V)
f osc
210
300
390
kHz
FEEDBACK AMPLIFIER
Voltage Feedback Input Threshold (Note 5)
VID0, VID1, VID2 and VID4 = “1” and VID3 = “0”
VID4 = “1” and VID0, VID1, VID2 and VID3 = “0”
Input Bias Current (V CM = 2.8 V)
Transconductance (V CM = 2.8 V, V COMP = 2.0 V)
Open Loop Voltage Gain (V COMP = 2.0 V)
Output Line Regulation (V CC = 4.5 to 5.5 V)
Output Load Regulation
V sense
I IB
G M
A VOL
Reg line
Reg load
1.764
2.744
3.43
?
400
?
?
?
1.8
2.8
3.5
20
800
67
7.0
5.0
1.836
2.856
3.57
?
1200
?
?
?
V
m A
m mho
dB
mV
mV
Output Current
m A
Source
Sink
I OH
I OL
?
?
120
120
?
?
PWM SECTION
Duty Cycle at G1 Output
%
Maximum
Minimum
DC max
DC min
77
?
88
?
95
0
Propagation Delay
Comp Input to G1 Output, T J = 25 ° C
Comp Input to G2 Output, T J = 25 ° C
t PLH1
t PLH2
?
?
0.1
0.1
?
?
m s
SOFT?START SECTION
Charge Current (V Soft?Start = 0 V)
Discharge Current under Current Limit (Note 6)
I chg
I SSIL
7.0
30
10
90
13
150
m A
m A
(V Soft?Start = 2.0 V, V sense = V out , V imax = V CC , V ifb = 0 V)
Discharge Current under Hard Current Limit
I SSHIL
40
64
?
mA
(V Soft?Start = 2.0 V, V sense < V out /2, V imax = V CC , V ifb = 0 V)
Hard Current Limit Hold Time
t SSHIL
100
200
300
m s
IMAX INPUT
Sink Current (V in max = V CC , V ifb = V CC )
I OL
133
190
247
m A
POWER GOOD OUTPUT
Threshold For Logic “1” to “0” Transition
V th
V sense
Upper Threshold
Lower Threshold
Response Time
Logic “0” to “1” (V sense changes from 0 V to V O )
Logic “1” to “0” (V sense changes from V O to 0 V)
t rPG
?
0.93
200
50
1.04
0.96
400
100
1.07
?
600
150
m s
Sink Current (V OL = 0.5 V)
Output Low Voltage (I OL = 100 m A) (Note 7)
I OLPG
V OLPG
?
?
10
250
?
500
mA
mV
FAULT OUTPUT
Threshold For Logic “0” to “1” Transition
V sense Response Time Switches from 2.8 V to V CC
Sink Current (V OL = 0.5 V)
V thF
t rF
I OLF
1.12
50
?
1.14
100
10
1.2
150
?
V ref
m s
mA
2.
3.
4.
5.
6.
Maximum package power dissipation limits must be observed.
Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
VID1, VID3, VID4 = logic 0, and VID0, VID2 = logic 1.
V sense is provided from a low impedance voltage source or shorted to the output voltage.
Under a typical soft current limit, the net soft?start discharge current will be 90 m A (I SSIL ) ? 10 m A (I chg ) = 80 m A. The soft?start sink to source
current ratio is designed to be 9:1.
7. Sense (Pin 6) = 5.0 V, Comp (Pin 10) open, VID4, VID2, VID1, VID0 = 1.0, VID3 = 0.
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