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| 型号： | MC3362P |
| 厂商： | MOTOROLA INC |
| 元件分类： | 接收器 |
| 英文描述： | Single Output LDO, 400mA, Fixed(2.5V), Low Noise, Fast Transient Response 8-MSOP -40 to 85 |
| 中文描述： | FM, AUDIO SINGLE CHIP RECEIVER, PDIP24 |
| 封装： | PLASTIC, DIP-24 |
| 文件页数： | 1/8页 |
| 文件大小： | 281K |
| 代理商： | MC3362P |
SEMICONDUCTOR
TECHNICAL DATA
LOW–POWER
DUAL CONVERSION
FM RECEIVER
Order this document by MC3362/D
P SUFFIX
PLASTIC PACKAGE
CASE 724
DW SUFFIX
PLASTIC PACKAGE
CASE 751E
(SO-24L)
X
X
X
Detector Output
Comparator Input
Comparator Output
VEE
2nd Mixer Input
2nd Mixer Input
2nd Mixer Output
1st Mixer Input
Quadrature Coil
Limiter
Decoupling
Limiter
Decoupling
2nd LO Emitter
1st Mixer Output
1st LO Output
1st LO Tank
1st LO Tank
Varicap Control
1st Mixer Input
2nd LO Output
2nd LO Base
VCC
Limiter Input
24
23
22
21
20
19
18
17
9
16
15
14
13
10
11
12
Meter Drive
8
7
6
5
1
2
3
4
Carrier Detect
Figure 2. Pin Connections and
Representative Block Diagram
Device
Operating
Temperature Range
Package
ORDERING INFORMATION
MC3362DW
MC3362P
TA = – 40 to +85
°
C
SO–24L
Plastic DIP
MOTOROLA ANALOG IC DEVICE DATA
. . . includes dual FM conversion with oscillators, mixers, quadrature
discriminator, and meter drive/carrier detect circuitry. The MC3362 also has
buffered first and second local oscillator outputs and a comparator circuit for
FSK detection.
Complete Dual Conversion Circuitry
Low Voltage: VCC = 2.0 to 6.0 Vdc
Low Drain Current (3.6 mA (Typical) @ VCC = 3.0 Vdc)
Excellent Sensitivity: Input Voltage 0.6
μ
Vrms (Typical)
for 12 dB SINAD
Externally Adjustable Carrier Detect Function
Low Number of External Parts Required
Manufactured Using Motorola s MOSAIC Process Technology
MC13135 is Preferred for New Designs
0.01
Recovered
Audio
8.2 k
0.001
VCC
Data
0.1
10 k
To PLL or Prescaler
1.0+
0.01
39 K
0.1
0.1
From PLL Phase
Detector
200 k
MC3362
RF Input
to 200 MHz
VCC
120 pF
10.245 MHz
50 pF
0.01
Input
Match
Ceramic Filter
455 kHz
0.1
Ceramic Filter
10.7 MHz
0.41
μ
H
To Carrier
Detect
Indicator
Lp = 680
μ
H
Cp = 180 pF
10 k
13
12
14
11
15
10
16
9
17
8
18
7
22
1
4
21
24
5
20
23
3
6
19
2
Figure 1. Simplified Application in a PLL Frequency
Synthesized Receiver
Figure 2.
Motorola, Inc. 1996
Rev 2
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