参数资料
型号: MC33689
厂商: 飞思卡尔半导体(中国)有限公司
英文描述: System Basis Chip with LIN transceiver(带LIN收发器的系统基片)
中文描述: 系统基础芯片(带林收发器的系统基片的LIN收发器)
文件页数: 6/18页
文件大小: 389K
代理商: MC33689
MC33689
6
Figure 2. SPI Timing characteristic
Note:
Incoming data at MOSI pin is sampled by the SBC at SCLK falling edge.
Outcoming data at MISO pin is set by the SBC at SCLK rising edge (after Tvalid delay time)
INT: output pin
Low Level Output Voltage (I
0
=1.5mA)
High Level Output Voltage (I
0
=-250uA)
Vol
0
0.9
V
Voh
Vdd-0.9
Vdd
WDC: window watchdog configuration pin
External resistor range
Rext
10
100
kohms
Watchdog period accuracy with external
resistor
Wdcacc
-15
15
%
Excluding resistor accuracy.
Note 1
Watchdog period with external resistor
Wdp 10
10.558
ms
R = 10 kohms. note 1
Watchdog period with external resistor
Wdp 100
99.748
ms
R = 100 kohms. note 1
Watchdog period without external resis-
tor, Conf pin open
note 1:
watchdog timing period calculation formula:
Twd = 0.991 * R + 0.648
(R in kohms and Twd in ms).
PWdoff
97
150
205
ms
Normal mode
HS1 and HS2: High side output pin
Rdson at Ta=25°C, and Iout -150mA
Ron25
2
2.5
Ohms
Vsup>9V
Rdson at Ta=125°C, and Iout -150mA
Ron125
4.5
Ohms
Vsup>9V
Rdson at Ta=125°C, and Iout -120mA
Ron3
3
Ohms
5.5<Vsup<9V
Output current limitation
Ilim
300
430
600
mA
Over temperature Shutdown
Ovt
155
190
°C
note 1
Leakage current
Ileak
10
uA
Output Clamp Voltage at Iout = -100mA
Vcl
-6
V
(V
s1
and V
s2
from 5.5V to 18V and T
amb
from -40°C to 125°C unless otherwise noted)
Description
Symbol
Characteristics
Unit
Conditions
Min
Typ
Max
Di 0
Do 0
Undefined
Don’t Care
Di 8
Don’t Care
Tlead
Tsih
Tsisu
Tlag
Tpclk
Twclkh
Twclkl
Tvalid
Do 8
Tsodis
CSB
SCLK
MOSI
MISO
Tsoen
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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