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| 型号： | MC33742DWR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 54/71页 |
| 文件大小： | 0K |
| 描述： | IC SYSTEM BASE W/LIN 28-SOIC |
| 标准包装： | 1,000 |
| 应用： | 自动 |
| 接口： | SPI |
| 电源电压： | 5.5 V ~ 18 V |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
| 配用： | KIT33742DWEVB-ND - KIT FOR 33742 SBC WITH EHSCAN |
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Analog Integrated Circuit Device Data
58
Freescale Semiconductor
33742
TYPICAL APPLICATIONS
C3:
47 F, ESR < 10
V2 REGULATOR: OPERATING WITH EXTERNAL BALLAST TRANSISTOR
The V2 regulator is a tracking regulator of the VDD output. Its accuracy relative to VDD is ±1.0%. It requires external
decoupling and stabilizing capacitors.
The recommended value are as follows:
22
F, ESR < 5.0
47
F, ESR < 10
The V2 pin has two functions: it is a sense input for the V2 regulator and is a 5.0 V power supply input to the CAN interface.
With respect to ballast transistor selection, either PNP or PMOS transistors may be used. A resistor between base and emitter
(or source and drain) is necessary to ensure proper operation and optimized performances. Recommended bipolar transistor is
MJD32C.
V2 REGULATOR: OPERATION WITHOUT BALLAST TRANSISTOR
The external ballast transistor is optional. If the application does not requires more than the maximum output current capability
of the VDD regulator, then the ballast transistor can be omitted. The thermal aspects must be analyzed as well.
The electrical connection is illustrated in Figure 32.
Figure 32. V2 Regulator Electrical Connection
FAILURE ON VDD, WDOG, RESET, AND INT PINS
The paragraphs below describe the behavior of the device and of the INT, RST, and WDOG pins at power-up and under failure
of the VDD regulator.
POWER-UP AND SBC ENTERING NORMAL OPERATION
After power-up the 33742 enters Normal Request mode (CAN interface is in TXRX mode): VDD is on and V2 is off.
After 350 ms if no watchdog is written (no TIM1 register write), a reset occurs and the 33742 returns to Normal Request mode.
During this sequence WDOG is active (low level).
Once watchdog is written, the 33742 goes to Normal mode: VDD is still on and V2 turns on, WDOG is no longer active, and
the RST pin is HIGH. If watchdog is not refreshed, the 33742 generates a reset and returns to Normal Request mode. Figure 33,
illustrates the operation.
VDD
VSUP
V2CTRL
RST
C3
C4
C1
C2
VDD
RESET
33742
V2
No Connect
Components List
C1: 22
F
C2: 100 nF
C3: >10
F
C4: 100 nF
MCU
VPWR
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