参数资料
型号: MC33794DWB
厂商: Freescale Semiconductor
文件页数: 13/18页
文件大小: 0K
描述: IC SENSOR ELECTRIC FIELD 54-SOIC
标准包装: 26
类型: 传感器接口
输入类型: 逻辑
输出类型: 逻辑
接口: ISO9141
电流 - 电源: 7mA
安装类型: 表面贴装
封装/外壳: 54-BSSOP(0.295",7.50mm 宽)裸露焊盘
供应商设备封装: 54-SOIC W EP
包装: 管件
Sensors
4
Freescale Semiconductor
MC33794
8
LAMP_SENSE
Lamp Sense
This terminal is normally connected to the LAMP_OUT terminal. The voltage at
this terminal is reduced and sent to LAMP_MON so the voltage at the lamp
terminal is brought into the range of the analog-to-digital converter (ADC) in the
MCU.
9
LAMP_MON
Lamp Monitor
This terminal is connected through a voltage divider to the LAMP_SENSE
terminal. The voltage divider scales the voltage at this terminal so that battery
voltage present when the lamp is off is scaled to the range of the MCU ADC.
With the lamp off, this terminal will be very close to battery voltage if the lamp is
not burned out and the terminal is not shorted to ground. This is useful as a lamp
check.
10
SHIELD_EN
Shield Driver
This terminal is used to enable the shield signal. The shield is disabled when
SHIELD_EN is a logic low (ground)
11–14
A, B, C, D
Selector Inputs
These input terminals control which electrode or reference is active. Selection
values are shown in Table 5, Electrode Selection, page 10. These are logic level
inputs.
15
SIGNAL
Undetected Signal
This is the undetected signal being applied to the detector. It has a DC level with
the low radio frequency signal superimposed on it. Care must be taken to
minimize DC loading of this signal. A shift of DC will change the center point of
the signal and adversely affect the detection of the signal.
16
LEVEL
Detected Level
This is the detected, amplified, and offset representation of the signal voltage on
the selected electrode. Filtering of the rectified signal is performed by a capacitor
attached to LP_CAP.
17
PWR_MON
Power Monitor
This is connected through a voltage divider to VPWR. It allows reduction of the
voltage so it will fall within the range of the ADC on the MCU.
18
LP_CAP
Low-Pass Filter Capacitor
A capacitor on this terminal forms a low pass filter with the internal series
resistance from the detector to this terminal. This terminal can be used to
determine the detected level before amplification or offset is applied. A 10 nF
capacitor connected to this terminal will smooth the rectified signal. More
capacitance will increase the response time.
19
R_OSC
Oscillator Resistor
A resistor from this terminal to circuit ground determines the operating frequency
of the oscillator. The MC33794 is optimized for operation around 120 kHz.
24
CLK
Clock
This terminal provides a square wave output at the same frequency as the
internal oscillator. The edges of the square wave coincide with the peaks
(positive and negative) of the sine wave.
25
VDD_MON
VDD Monitor
This is connected through an internal voltage divider to VDD REG. It allows
reduction of the voltage so it will fall within the range of the ADC on the MCU.
26
VDD
VDD Capacitor
A capacitor is connected to this terminal to filter the internal analog regulated
supply. This supply is derived from VPWR through internal VDD REG.
27
VPWR
Positive Power Supply
12 V power applied to this terminal will be converted to the regulated voltages
needed to operate the part. It is also converted to 5.0 V (internal VCC REG) and
8.5 V (internal VDD REG) to power the MCU and external devices.
28
VCC
5.0 V Regulator Output
This output terminal requires a 47 F capacitor and internal VCC REG provides
a regulated 5.0 V for the MCU and for internal needs of the MC33794.
29
AGND
Analog Ground
This terminal is connected to the ground return of the analog circuitry. This
ground should be kept free of transient electrical noise like that from logic
switching. Its path to the electrical current return point should be kept separate
from the return for GND.
30
SHIELD
Shield Driver
This terminal connects to cable shields to cancel cable capacitance.
Table 1. SOICW-EP TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
Name
Formal Name
Definition
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