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| 型号： | MC33884DW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 19/21页 |
| 文件大小： | 0K |
| 描述： | IC SWITCH SDI MONITOR 24-SOIC |
| 标准包装： | 30 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 24-SOIC |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33884
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TC ≤ 105°C, unless otherwise
noted. Typical values, where applicable, reflect the approximate parameter mean with VPWR = 13 V, TA = 25°C under nominal
conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT TIMING
Pulse Wetting Current Duration
tPULSE
3.0
34
43
ms
Interrupt Delay Time
tINT(DELAY)
2.5
—
13
ms
SCLK Frequency vs. SO Load Capacitance
200 pF
160 pF
120 pF
fSCLK
3.2
3.5
4.0
—
MHz
DIGITAL INTERFACE TIMING
Input Logic Voltage Thresholds (13)
VIN(LOGIC)
0.2 x VDD
—
0.7 x VDD
V
SO High State Output Voltage (IOH = 1 mA)
VOH(SO)
3.5
—
V
SO Low State Output Voltage (IOL = 1 mA)
VOL(SO)
—
0.4
V
SO Tri-State Leakage Current (CS = 0.7 VDD, VSO = 0 to VDD)
IT(SO)
-40
—
40
A
SI Pull Down Current (SI = VDD)
ISI
5.0
—
35
A
SCLK Input Current (0 V = VDD)
ISCLK
-10
—
10
A
CS Pull-Up Current (CS = 0 V)
ICS
-25
—
-5.0
A
RST Pull Down Current (RST = 0 V)
IRST
5.0
—
35
A
INT Low State Output Voltage (IOL = 0.5 mA)
VOL(INT)
—
0.4
V
Input Capacitance on SCLK, SI, Tri-State, SO, CS (13)
CIN
—
20
pF
Falling Edge of CS to Rising Edge of SCLK (13) (Required set-up time)
tLEAD
—
100
140
ns
Falling Edge of SCLK to Rising Edge of CS (Required set-up time)
tLAG
—
50
ns
SI to Rising Edge of SCLK (Required set-up time)
tSU2
—
25
45
ns
Rising Edge of SCLK to SI (Required hold time)
tH2
—
25
45
ns
SO to Rising Edge of SCLK
tSU1
90
125
—
ns
Rising Edge of SCLK to Falling Edge of SO (Hold time)
tH1
90
125
—
ns
SO Rise Time, SO Fall Time (CL = 200 pF)
tR(SO)
tF(SO)
—
30
50
ns
SI, CS, SCLK Incoming Signal Rise Time (13)
tR(SI)
—
50
ns
SI, CS, SCLK Incoming Signal Fall Time (13)
tF(SI)
—
50
ns
Time from Falling Edge of CS to SO Low Impedance (13)
tSO(EN)
—
80
110
ns
Notes
9
Upper and lower logic threshold voltage levels apply to SI, CS, SCLK, RST, SYNC, MASL. See page five.
10
This parameter is guaranteed by design, however, it has not been production tested.
11
Rise and fall time for incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
12
Time required for output states data to be available at SO pin.
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