参数资料
| 型号： | MC33897D |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 5/19页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCEIVER CAN SW 14-SOIC |
| 标准包装： | 55 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | CAN |
| 电源电压： | 12V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 管件 |
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33897
FUNCTIONAL DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM COMPONENTS
VBATT INPUT
This power input is not reverse battery protected and
should use an external diode to protect it from damage due
to reverse battery if this protection is desired. The voltage
drop of the diode must be taken into consideration when the
operating range of the system is being determined. This
diode is generally used to protect the entire module from
reverse battery and should be selected accordingly.
BUS I/O
This input/output may require electrostatic discharge
(ESD) and/or EMI external circuitry. A set of components is
shown in the simplified application diagrams on page 15. The
value of the capacitor should be adjusted downward in direct
proportion to the added capacitance of the ESD or EMI
circuits. The series resistance of the inductor should be kept
below 3.5
Ω to prevent its voltage drop from significantly
degrading system noise margins.
FUNCTIONAL BLOCK DIAGRAM COMPONENTS
TIMER OSC
This circuit generates a 500 kHz signal to be used for
internal logic. It is the reference for some of the required
delays.
TIMERS
This circuit contains the timing logic used to hold the CNTL
active for the required time after the conditions for sleep
mode have been met. It is also used to keep the TXD driver
active for a period of time after it has generated a passive
level on the bus.
MODE CONTROL
This circuit contains the control logic for the various
operating modes and conditions required for the IC.
BUS RCVR
This circuit translates the levels on the BUS pin to a CMOS
level indicating the presence of a logic [0] or a logic [1]. It also
determines the presence of a high voltage wake-up (HVWU)
signal that is passed to Mode Control and Timers circuits. An
analog filter is used to “de-glitch” the high voltage wake-up
signal and prevent false exits from the Sleep mode.
TXD BUS DRVR
This circuit drives the BUS. It can drive it with the higher
voltage wake-up signals when enabled by the Mode Control
circuit. It can also provide waveshaping for reduced EMI or
not provide it for the higher data rate mode. The actual data
is received on TXD at CMOS logic levels, then translated by
this circuit to the necessary operating voltages.
UNDER-VOLTAGE DETECT
This circuit monitors internal operating voltage to assure
proper operation of the part. If a low-voltage condition is
detected, it sends a signal to disable the BUS RCVR and
TXD BUS DRVR circuits. This prevents incorrect data from
being put on the bus or sent to the MCU.
LOAD SWITCH
The LOAD switch provides a path for an external resistor
connected to the BUS to be connected to ground. When a
loss of ground is detected, this switch is opened to prevent
the current that would normally be flowing to the ground from
the module from going back through the load resistor and
raising the bus level. The circuit is opened when the voltage
between GND and VBATT becomes too low as would be the
case if module ground were lost.
BUS LOADING PARAMETERS
Figure 6. Transmitter Delays in Normal and Transmit High Voltage Wake-up Modes
47
μH
1.0 k
Ω
CNOM = 100 pF + (n -1) 220 pF
R
=
6.49 k
Ω
(n -1)
33897
6.49 k
Ω
BUS
LOAD
GND
100 pF
VBATT
Note: The letter ’n’ represents the number of nodes in the system.
BUSMOD
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