参数资料
型号: MC34161DMR2
厂商: ON Semiconductor
文件页数: 12/18页
文件大小: 0K
描述: IC MONITOR VOLTAGE UNIV 8MICRO
产品变化通告: LTB Notification 03/Jan/2008
标准包装: 1
类型: 多压监控器
监视电压数目: 2
输出: 开路漏极或开路集电极
复位: 低有效
电压 - 阀值: 可调节/可选择
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: Micro8?
包装: 剪切带 (CT)
其它名称: MC34161DMR2OSCT
MC34161, MC33161, NCV33161
V CC
8
R A
Input V S
V 2
V Hys
V S
1
2.54V
Reference
Piezo
V 1
-
R 2
7
+
+
Output
Voltage
Pins 5, 6
GND
V CC
GND
Osc `ON'
R 1
2 +
3 +
+
-
1.27V
+
-
+
2.8V
-
+
0.6V
6
5
1.27V
4
C T
R B
The above figure shows the MC34161 configured as an overvoltage detector with an audio alarm. Channel 1 monitors input voltage V S while channel 2 is connected
as a simple RC oscillator. As the input voltage increases from ground, the output of channel 1 allows the oscillator to turn ‘ON’ when V S exceeds V 2 .
For known resistor values, the voltage trip points are:
For a specific trip voltage, the required resistor ratio is:
V 1 + (V th * V H )
R 2
R 1
) 1 V 2 + V th
R 2
R 1
) 1
R 2
R 1
+
V 1
V th * V H
* 1
R 2
R 1
+
V 2
V th
* 1
Figure 24. Overvoltage Detector with Audio Alarm
V CC
8
2.54V
Input V S
V 2
V 1
V Hys
1
Reference
-
R 3
7
+
+
Output
Voltage
Pin 5
GND
V CC
GND
R 2
V S
2 +
+
-
1.27V
+
2.8V
-
+
6
R DLY
Output
Voltage
Pin 6
V CC
GND
Reset LED `ON'
t DLY
R 1
3 +
+
-
1.27V
4
0.6V
5
C DLY
The above figure shows the MC34161 configured as a microprocessor reset with a time delay. Channel 2 monitors input voltage V S while channel 1 performs the
time delay function. As the input voltage decreases towards ground, the output of channel 2 quickly discharges C DLY when V S falls below V 1 . As the input voltage
increases from ground, the output of channel 2 allows R DLY to charge C DLY when V S exceeds V 2 .
For known resistor values, the voltage trip points are:
For a specific trip voltage, the required resistor ratio is:
V 1 + (V th * V H )
R 2
R 1
) 1
V 2 + V th
R 2
R 1
) 1
R 2
R 1
+
V 1
V th * V H
* 1
R 2
R 1
+
V 2
V th
* 1
For known R DLY C DLY values, the reset time delay is:
t DLY = R DLY C DLY In
1 ?
1
V th
V CC
Figure 25. Microprocessor Reset with Time Delay
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