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参数资料
| 型号： | MC34702EKR2 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 17/39页 |
| 文件大小： | 0K |
| 描述： | IC POWER SUPPLY MCU 3A 32-SOIC |
| 标准包装： | 1 |
| 应用： | 电源 |
| 电流 - 电源： | 60mA |
| 电源电压： | 2.8 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 32-SOIC |
| 包装： | 剪切带 (CT) |
| 配用： | KIT33702DWBEVB-ND - KIT FEATURES THE MC34701 |
| 其它名称： | MC34702EKR2CT |
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FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
POWER SUPPLY PIN (VDDI)
Internal supply voltage. A ceramic low ESR 1uF 6V X5R or
X7R capacitor is recommended.
ADDRESS PIN (ADDR)
The ADDR pin is used to set the address of the device
when used in an I 2 C communication. This pin can either be
tied to VDDI or grounded through a 10k ? resistor. Refer to
pin.
ENABLE 1 AND 2 PINS (EN1 AND EN2)
These two pins permit positive logic control of the Enable
function and selection of the Power Sequencing Mode
concurrently. Table 5 depicts the EN1 and EN2 function and
Power Sequencing Mode selection.
Both EN1 and EN2 pins have internal pull-down resistors
and both can withstand a short circuit to the supply voltage,
6.0V.
RESET TIMER PIN (RT)
The Reset Timer power-up delay (RT) pin is used to set
the delay between the time when the LDO and switcher
outputs are active and stable and the RST output is released.
An external resistor and capacitor are used to program the
timer. The power-up delay can be obtained by using the
following formula:
t D = 10ms + R t C t
Where R t is the Reset Timer programming resistor and C t
is the Reset Timer programming capacitor, both connected in
parallel from RT to ground.
Note Observe the maximum C t value and expect reduced
accuracy if R t is less than 10k ? .
RESET OUTPUT PIN ( RST )
The reset control circuit monitors both the switching
regulator and the LDO feedback voltages. It is an open drain
output and has to be pulled up to some supply voltage (e.g.,
the output of the LDO) by an external resistor.
The reset control circuit supervises both output voltages—
Table 5.
Operating Mode Selection
the linear regulator output V LDO and the switching regulator
EN1
0
0
1
1
EN2
0
1
0
1
Operating Mode
Regulators Disabled
Standard Power Sequencing
Inverted Power Sequencing
No Power Sequencing,
Regulators Enabled
output V OUT . When either of these two regulators is out of
regulation (high or low), the RST pin is pulled low. There is a
20 ? s delay filter preventing erroneous resets. During power-
up sequencing, RST is held low until the Reset Timer times
out.
CLOCK SELECTION PIN (CLKSEL)
This pin sets the CLKSYN pin as either an oscillator output
or a synchronization input pin. The CLKSEL pin is also used
for the I 2 C address selection.
CLOCK SYNCHRONIZATION PIN (CLKSYN)
Oscillator output/synchronization input pin.
34702
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
17
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