参数资料
型号: MC34712EPR2
厂商: Freescale Semiconductor
文件页数: 14/24页
文件大小: 0K
描述: IC CONVERTER DDR 24QFN
标准包装: 2,500
应用: 转换器,DDR
输入电压: 3 V ~ 6 V
输出数: 1
输出电压: 0.7 V ~ 1.35 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN 裸露焊盘(4x4)
包装: 带卷 (TR)
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SD = 0 &
STBY=x
Shutdown
V TT = Discharge
V REF = Discharge
V IN < 3.0 V
Power Off
V TT =OFF
V REF =OFF
PG = 1
SD = 1 &
STBY=0
Standby
V TT = OFF
V R EF = ON
V TT >V OV
PG = 1
SD = 1 &
STBY=1
3.0 V<=V IN <=6.0 V
SD = 1 &
STBY=1
PG = 1
I OUT >=I SHORT
Over-voltage
V TT =ON
V REF =ON
PG = 1
V TT <V OV
V TT >V UV
Normal
V TT = ON
V REF =ON
PG = 0
T J <=145°C
T IMEOUT Expired
T IMEOUT
Expired
T IMEOUT
Expired
Short-circuit
V TT =OFF
V REF =OFF
PG = 1
V TT <V UV
Under-voltage
V TT =ON
V REF =ON
PG = 1
Thermal Shutdown
V TT =OFF
V R EF =OFF
PG = 1
Over-current
V TT =OFF
V RE F =ON
PG = 1
I OUT1 >=I LIM1
For>=10 ms
T J >= 170°C
Figure 6. Operation Modes Diagram
MODES OF OPERATION
The 34712 has three primary modes of operation:
Normal Mode
In normal mode, all functions and outputs are fully
operational. To be in this mode, the V IN needs to be within its
operating range, both Shutdown and Standby inputs are
high, and no faults are present. This mode consumes the
most amount of power.
Standby Mode
This mode is predominantly used in Desktop memory
solutions where the DDR supply is desired to be ACPI
compliant (Advanced Configuration and Power Interface).
When this mode is activated by pulling the STBY pin low, V TT
is put in High Z state, I OUT = 0 A, and V REF stays active. This
is the S3 state Suspend-To-Ram or Self Refresh mode and it
is the lowest DRAM power state. In this mode, the DRAM will
preserve the data. While in this mode, the 34712 consumes
less power than in the normal mode, because the buck
converter and most of the internal blocks are disabled.
Shutdown Mode
In this mode, activated by pulling the SD pin low, the chip
is in a shutdown state and the outputs are all disabled and
discharged. This is the S4/S5 power state or Suspend-To-
Disk state, where the DRAM will loose all of its data content
(no power supplied to the DRAM). The reason to discharge
the V TT and V REF lines is to ensure upon exiting, the
Shutdown Mode that V TT and V REF are lower than V DDQ ,
otherwise V TT can remain floating high, and be higher than
V DDQ upon powering up. In this mode, the 34712 consumes
the least amount of power since almost all of the internal
blocks are disabled.
START-UP SEQUENCE
When power is first applied, the 34712 checks the status
of the SD and STBY pins. If the device is in a shutdown mode,
no block will power up and the output will not attempt to ramp.
If the device is in a standby mode, only the V DDI internal
supply voltage and the bias currents are established and no
further activities will occur. Once the SD and STBY pins are
released to enable the device, the internal V DDI POR signal is
also released. The rest of the internal blocks will be enabled
34712
Analog Integrated Circuit Device Data ?
14
Freescale Semiconductor
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