参数资料
型号: MC35XS3400CPNA
厂商: Freescale Semiconductor
文件页数: 14/46页
文件大小: 0K
描述: IC SWITCH QUAD HI SIDE 24-QFN
标准包装: 168
类型: 高端开关
输出数: 4
Rds(开): 35 毫欧
内部开关:
电流限制: 5A
输入电压: 6 V ~ 20 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 24-PowerQFN
供应商设备封装: 24-PQFN(12x12)
包装: 托盘
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 6.0 V ? V PWR ? 20 V, 3.0 V ? V DD ? 5.5 V, - 40 ? C ? T A ? 125 ? C, GND = 0 V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25 °C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Bulb Cooling Time Step
ms
CB[1:0]=00 or 11 (medium)
CB[1:0]=01 (fast)
t BC1_00
t BC2_00
t BC3_00
t BC4_00
t BC5_00
t BC6_00
t BC1_01
t BC2_01
t BC3_01
t BC4_01
t BC5_01
t BC6_01
582
312
356
416
502
628
296
156
176
202
256
452
834
448
510
596
718
898
418
224
254
290
360
648
1084
584
664
776
934
1168
544
292
332
378
468
884
CB[1:0]=10 (slow)
t BC1_10
t BC2_10
t BC3_10
t BC4_10
t BC5_10
t BC6_10
1166
624
714
834
1002
1256
1668
894
1022
1192
1434
1796
2170
1164
1310
1552
1866
2340
PWM MODULE TIMING
Input PWM Clock Range on IN0
f IN0
7.68
30.72
kHz
Input PWM Clock Low Frequency Detection Range on
Input PWM Clock High Frequency Detection Range on
IN0 (34)
IN0 (34)
f IN0(LOW)
f IN0(HIGH)
1.0
100
2.0
200
4.0
400
kHz
kHz
Output PWM Frequency Range
Output PWM Frequency Accuracy using Calibrated Oscillator
Default Output PWM Frequency using Internal Oscillator
CS Calibration Low Minimum Time Detection Range
CS Calibration Low Maximum Tine Detection Range
f PWM
A FPWM(CAL)
f PWM(0)
t CSB(MIN)
t CSB(MAX)
-10
84
14
140
120
20
200
1.0
+10
156
26
260
kHz
%
Hz
? s
? s
Output PWM Duty-cycle Range for f PWM = 400
Hz (35)
R PWM _400
10
98
%
Output PWM Duty-cycle Range for f PWM = 200 Hz
R PWM _200
5.0
98
%
Output PWM Duty-cycle Range for f PWM = 1.0 kHz for high speed slew rate
R PWM _1k
6.0
94
%
INPUT TIMING
Direct Input Toggle Timeout
t IN
175
250
325
ms
AUTO-RETRY TIMING
Auto-retry Period
t AUTO
105
150
195
ms
Notes
34. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].
35. The PWM ratio is measured at V HS = 50% of V PWR and for the default SR value. It is possible to put the device fully-on (PWM duty-cycle
100%) and fully-off (duty-cycle 0%). For values outside this range, a calibration is needed between the PWM duty-cycle programming
and the PWM on the output with R L = 5.0 ? resistive load.
35XS3400
Analog Integrated Circuit Device Data ?
14
Freescale Semiconductor
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