参数资料
| 型号： | MC44605PG |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBK ISO PWM 16DIP |
| 产品变化通告： | Product Obsolescence 19/Dec/2008 |
| 标准包装： | 500 |
| 系列： | GreenLine™ |
| PWM 型： | 电流模式 |
| 输出数： | 1 |
| 频率 - 最大： | 250kHz |
| 占空比： | 80% |
| 电源电压： | 10 V ~ 15 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 是 |
| 工作温度： | -25°C ~ 85°C |
| 封装/外壳： | 16-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 其它名称： | MC44605PGOS |
MC44605
In effect, the output of the latch L1 is:
V ref
DISCH
&
VS Latch
C T <1.6 V
sync
S Q
L1
R
DISCH
— high during the oscillator capacitor charge and during
the REGUL phase
— low for the oscillator capacitor discharge
Now, the latch L2 is set when the L1 output is high and the
synchronization condition is performed (that is: sync = 1 ?
free mode or synchro signal high state) and during the
dead ? time (V DT high). So, this latch is set for the C T charge.
On the other hand, this latch is reset by the signal used to
reset L1. Consequently, it is reset at the end of the charge
phase.
So, in any case, Q L2 is:
— high during the C T charge cycle
— low in the other cases
Thus, this latch enables to obtain a signal that is high for
the charge phase and low in the other cases, whatever the
mode (synchronized or free) and whatever the
synchronization pulses width (higher than the delay
necessary for the oscillator to reach its intermediary value or
lower than this delay) in the synchronized mode.
10
C T
Vint
3.6 V
1.6 V
I charge
C OSCINT
sync
C OSC HIGH
C OSCINT
C OSC LOW
DISCH
R
&
&
Sf
PWM
Latch
Output
&
PWM
Set
Q L2
V DT (from demag
block)
& S Q
L2
Q
That is why:
— the discharge current source must be connected to the
C OSC REGUL
oscillator capacitor when Q L1 is low. The condition (C T
voltage higher than the valley value) is added to stop
1
0
1
Q L2
the discharge phase as soon as the oscillator voltage is
detected as lower than the valley value (without any
delay due to the L1 latch propagation time).
— the REGUL current source must be connected when:
? Q L1 is high (charge or REGUL phase)
? Q L2 is low (the oscillator is not in a charge phase)
On the other hand, the oscillator charge is stopped when:
— the oscillator voltage reaches the peak value in the
0
&
I regul
MC44605
Figure 5. Oscillator
I discharge
free mode
— the oscillator voltage is higher than the intermediary
value (V int ) and the synchronization signal is negative,
in the synchronized mode.
Consequently, in any case, Q L2 that is high during the
oscillator charge phase, is high for the delay during which
the oscillator voltage grows from the valley value up to the
intermediary one. That is why the signal Sf (refer to the MPL
block) that must be high when the oscillator voltage is
between the valley value and the intermediary one during
the charge phase (Q L2 high), is obtained using an AND gate
with the following inputs:
— Q L2 (Q L2 high <=> charge phase)
— C OSCINT (C OSCINT high <=> the C T voltage is lower
than the intermediary value).
So, using the output of this AND gate, Sf is obtained.
This signal Sf is connected to a logic block consisting of
two AND gates and an OR one. This block aims at supplying
a signal VS that:
— gets high as soon as Sf becomes high if the PWM
latch output is low
— gets low as soon as the PWM latch is set and then
Synchronization Section (Note 1)
The synchronization block consists of a protection
arrangement similar to the demagnetization block one (a
diode + a negative active clamping system (Note 2)). In
addition to this, a high value resistor (R ? about 50 k W ) is
incorporated as the pin 9 input is also used by the EHTOVP
section.
The signal obtained at the output of this protection
arrangement, is compared to a negative threshold ( ? 200 mV,
typically) so that when the synchronization pulse applied to
the pin 9 (through a resistor or a resistors divider to adapt this
input to the EHTOVP function), is higher than this
threshold, the system considers that the synchronization
condition is performed (free mode or synchronization signal
high level).
Note 1. The synchronization can be inhibited by connecting the
pin 9 to the ground. By this means, a free mode is
obtained.
Note 2. This negative active clamping system works even if the
circuit is off. This feature is really useful as
synchronization pulses may be applied while the product
is off.
remains low until the next cycle.
http://onsemi.com
12
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