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参数资料
| 型号： | MC44827 |
| 厂商： | Motorola, Inc. |
| 英文描述： | LOW-POWER PLL TUNING CIRCUIT |
| 中文描述： | 低功耗锁相环调谐电路 |
| 文件页数： | 6/8页 |
| 文件大小： | 157K |
| 代理商： | MC44827 |
MC44827/27B
6
MOTOROLA ANALOG IC DEVICE DATA
Definition of Permissible Bus Protocols
1. Bus Protocol for 18 Bit
B3 B2 B1 B0 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3
N2 N1 N0
Max Counting Ratio 16363
N14 is Reset Internally
2. Bus Protocol for 19 Bit
B3 B2 B1 B0 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4
N3 N2 N1 N0
Max Counting Ratio 32767
B0 to B3: Control of Band Buffers
N0 to N14: Programmable Divider Counting Ratio
N14 = MSB; N0 = LSB
Minimum Counting Ratio Always 17
B3 = First Shifted Bit
N0 = Last Shifted Bit
3. Bus Protocol for Test and Further Features (34 Bit)
B3 B2 B1 B0 N14
…
N0 Y6 T5 T4 Y3 T2 T1 T0 X7
X6
…
X1 X0
T0 to T2: Control the Phase Comparator (Note 1)
T4: Switches Test Signals to the Buffer Outputs
T5: Division Ratio of the Reference Divider
B Version T5 = “X”
– X0 to X7: Are Random
– Y3 and Y6: Are Not Used
B3 = First Shifted Bit
X0 = Last Shifted Bit
Definition of the Bits for Test and Features
Bit T0: Defines the Charge Pump Current of the
Bit T0:
Phase Comparator
T0 = 0
T0
= 1
Pump Current 15
μ
A Typical
Pump Current 50
μ
A Typical
Bits T1 and T2: Define the Digital Function of the Phase
Bits T1 and T2:
Comparator
T2
T1
State
Output Function of Phase Comparator
0
0
1
Normal Operation
0
1
2
High Impedance (3–State)
1
0
3
Upper Source “On”, Lower Source “Off”
1
1
4
Lower Source “On”, Upper Source “Off”
NOTE:
1. The phase comparator pulls high if the input frequency is too
high and it pulls low when the input frequency is too low.
(Inversion by Operational Amplifier) The phase comparator
generates a fixed duration offset pulse for each comparison
pulse. This guarantees operation in the linear region.
The offset pulse is a positive current pulse (upper source).
Bit T4: Switches the Internal Frequencies Fref and
Bit T4:
FBY2 to the Buffer Outputs (B2, B3)
T4 = 0
T4
= 1
Fref Switched to Buffer Output B2
FBY2 Switched to Buffer Output B3
Normal Operation
NOTE
:
Bits B2 and B3 have to be one in this case.
Fref is the reference frequency.
FBY2 is the output frequency of the programmable divider,
divided by two.
Figure 6. Equivalent Circuit of the Integrated
Band Buffers
“On”/“Off”
ISUB
30 mA (40 mA
at 0 to 80
°
C)
VCC3 12 V
20
…
25 V
Protection
IB
Out
B0
…
B3
NOTES:
IB + ISUB = 5.5 mA Typical
IB = Base Current
ISUB = Substrate Current of PNP
Gnd
Saturation Voltage
0.15 V Typical
0.3 V Max
Bit T5: Defines the Division Ratio of the Reference
Bit T5:
Divider
T5 = 0
T5
= 1
Division Ratio 1024
Division Ratio 512
NOTE:
The division ratio of the reference divider can only be
programmed in the 34 bit bus protocol.
In the standard bus protocol the division ratio is 512.
(The power–up reset POR sets the division ratio to 512).
On “B–version”, T5 = “X”. Division ratio 1024 is fixed.
OPERATING DESCRIPTION
Introduction
A representative block diagram and typical system
application are shown in Figures 1 and 8. A discussion of the
features and function of each of the internal blocks is given.
The Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14 + 8132 x N13 +
…
+ 4 x N2 + 2 x N1 + N0
Maximum Ratio 32767
(16363 in case of 18 bit bus protocol)
Minimum Ratio 17
N0
…
N14 are the different bits for frequency information.
At power–on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
The divide by 8 prescaler has a preamplifier which
guarantees high input sensitivity.
The Phase Comparator
The phase comparator is both phase and frequency
sensitive and has very low output leakage current in the high
impedance state.
Lock Detector
The lock–detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
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