参数资料
型号: MC56F8013VFAE
厂商: Freescale Semiconductor
文件页数: 101/126页
文件大小: 0K
描述: IC DIGITAL SIGNAL CTLR 32-LQFP
标准包装: 250
系列: 56F8xxx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 32MHz
连通性: I²C,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 26
程序存储器容量: 16KB(8K x 16)
程序存储器类型: 闪存
RAM 容量: 2K x 16
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 32-LQFP
包装: 托盘
产品目录页面: 734 (CN2011-ZH PDF)
配用: CPA56F8013-ND - BOARD SOCKET FOR MC56F8013
APMOTOR56F8000E-ND - KIT DEMO MOTOR CTRL SYSTEM
DEMO56F8013-EE-ND - BOARD DEMO FOR 56F8013
56F8013/56F8011 Data Sheet, Rev. 12
76
Freescale Semiconductor
00 = PWM5 — PWM5 Output (default)
01 = PWM5 — PWM5 Output
10 = FAULT2 — PWM FAULT2 Input
11 = T3 — Timer Channel 3 input/output
6.3.8.13
Configure GPIOA4[1:0] (CFG_A4)—Bits 1–0
These bits select the alternate function for GPIOA4.
00 = PWM4 — PWM4 Output (default)
01 = PWM4 — PWM4 Output
10 = FAULT1— PWM FAULT1 Input
11 = T2 — Timer Channel 2 input/output
NOTE:
Take care when programming the following CFG_* signals so as not to connect
two different I/O pins to the same peripheral input. For example, do not set
CFG_B7 to select SCL and also set CFG_B0 to select SCL. If this occurs for an
output signal, then the signal will be routed to two I/O pins. For input signals, the
values on the two I/O pins will be ORed together before reaching the peripheral.
6.3.9
Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip. The
corresponding peripheral should itself be disabled while its clock is shut off.
Figure 6-11 Peripheral Clock Enable Register (SIM_PCE)
6.3.9.1
I2C Clock Enable (I2C)—Bit 15
0 = The clock is not provided to the I2C module(the 12C module is disabled)
1 = Clocks to the I2C module are enabled
6.3.9.2
Reserved—Bit 14
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.3.9.3
Analog-to-Digital Converter IPBus Clock Enable (ADC)—Bit 13
0 = The clock is not provided to the ADC module (the ADC module is disabled)
1 = Clocks to the ADC module are enabled
Base + $C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
I2C
0
ADC
0
TMR
0
SCI
0
SPI
0
PWM
Write
RESET
0
00
0
000
0
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