10
56F8355 Technical Data
Preliminary
1.5 Product Documentation
The documents listed in Table 1-2 are required for a complete description and proper design with
the 56F8355. Documentation is available from local Motorola distributors, Motorola
semiconductor
sales
offices,
Motorola
Literature
Distribution
Centers,
or
online
at
http://www.motorola.com/semiconductors.
Table 1-1 Bus Signal Names
Name
Function
Program Memory Interface
pdb_m[15:0]
Program data bus for instruction word fetches or read operations.
cdbw[15:0]
Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus
are used for writes to program memory.)
pab[20:0]
Program memory address bus. Data is returned on pdb_m bus.
Primary Data Memory Interface Bus
cdbr_m[31:0]
Primary core data bus for memory reads. Addressed via xab1 bus.
cdbw[31:0]
Primary core data bus for memory writes. Addressed via xab1 bus.
xab1[23:0]
Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written
on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O.
1.
Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0.
Secondary Data Memory Interface
xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads.
xab2[23:0]
Secondary data address bus used for the second of two simultaneous accesses. Capable of
addressing only words. Data is returned on xdb2_m.
Peripheral Interface Bus
IPBus [15:0]
Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate
as the Primary Data Memory and therefore generates no delays when accessing the processor.
Write data is obtained from cdbw. Read data is provided to cdbr_m.
Table 1-2 56F8355 Chip Documentation
Topic
Description
Order Number
DSP56800E
Reference Manual
Detailed description of the 56800E family architecture,
and 16-bit hybrid controller core processor and the
instruction set
DSP56800ERM/D
568300 Peripheral User
Manual
Detailed description of peripherals of the 56F8300
devices
MC56F8300UM/D
56F8300 SCI/CAN
Bootloader User Manual
Detailed description of the SCI/CAN Bootloaders
56F8300 family of devices
MC56F83xxBLUM/D
56F8355
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
MC56F8355/D
56F8355
Product Brief
Summary description and block diagram of the
56F8355 core, memory, peripherals and interfaces
MC56F8355PB/D
56F8355 Errata
Details any chip issues that might be present
MC56F8355E/D