
80
MC68331TS/D
FOC[5:1] — Force Output Compare
0 = Has no meaning
1 = Causes pin action programmed for corresponding OC pin, but the OC flag is not set.
FOC[5:1] correspond to OC[5:1].
FPWMA — Force PWMA Value
0 = Normal PWMA operation
1 = The value of F1A is driven out on the PWMA pin, regardless of the state of PPROUT.
FPWMB — Force PWMB Value
0 = Normal PWMB operation
1 = The value of F1B is driven out on the PWMB pin.
PPROUT — PWM Clock Output Enable
0 = Normal PWM operation on PWMA
1 = TCNT clock driven out PWMA pin
PPR[2:0] — PWM Prescaler/PCLK Select
This field selects one of seven prescaler taps, or PCLK, to be PWMCNT input.
SFA — PWMA Slow/Fast Select
0 = PWMA period is 256 PWMCNT increments long.
1 = PWMA period is 32768 PWMCNT increments long.
SFB — PWMB Slow/Fast Select
0 = PWMB period is 256 PWMCNT increments long.
1 = PWMB period is 32768 PWMCNT increments long.
The following table shows the effects of SF settings on PWM frequency for a 16.78-MHz system clock
and a 20.97-MHz system clock.
F1A — Force Logic Level One on PWMA
0 = Force logic level zero output on PWMA pin
1 = Force logic level one output on PWMA pin
PPR[2:0]
System Clock
Divide-By Factor
000
2
001
4
010
8
011
16
100
32
101
64
110
128
111
PCLK
PPR[2:0]
Prescaler Tap
SFA/B = 0
SFA/B = 1
16.78 MHz
20.97 MHz
16.78 MHz
20.97 MHz
16.78 MHz
20.97 MHz
000
Div 2 = 8.39 MHz
Div 2 = 10.5 MHz
32.8 kHz
41 kHz
256 Hz
320 Hz
001
Div 4 = 4.19 MHz
Div 4 = 5.25 MHz
16.4 kHz
20.5 kHz
128 Hz
160 Hz
010
Div 8 = 2.10 MHz
Div 8 = 2.62 MHz
8.19 kHz
10.2 kHz
64.0 Hz
80.0 Hz
011
Div 16 = 1.05 MHz
Div 16 = 1.31 MHz
4.09 kHz
5.15 kHz
32.0 Hz
40.0 Hz
100
Div 32 = 524 kHz
Div 32 = 655 kHz
2.05 kHz
2.56 kHz
16.0 Hz
20.0 Hz
101
Div 64 = 262 kHz
Div 64 = 328 kHz
1.02 kHz
1.28 kHz
8.0 Hz
10.0 Hz
110
Div 128 = 131 kHz
Div 128 = 164 kHz
512 Hz
641 Hz
4.0 Hz
5.0 Hz
111
PCLK
PCLK/256
PCLK/32768
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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