参数资料
型号: MC68331CPV20B1
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 20 MHz, MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-144
文件页数: 18/90页
文件大小: 481K
代理商: MC68331CPV20B1
MC68331
MOTOROLA
MC68331TS/D
25
Port width is the maximum number of bits accepted or provided during a bus transfer. External devices
must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,
the address space, the size of the transfer, and the type of cycle. The selected device controls the length
of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity
of an address and provide timing information for data. The EBI operates in an asynchronous mode for
any port width.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic can be synchro-
nized with EBI transfers. Chip-select logic can also provide internally-generated bus control signals for
these accesses. Refer to 3.5 Chip Selects for more information.
3.4.1 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the
beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals. The
size signals indicate the number of bytes remaining to be transferred during an operand cycle. They are
valid while the address strobe (AS) is asserted. The following table shows SIZ0 and SIZ1 encoding. The
read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes
state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only chang-
es state when a write cycle is preceded by a read cycle or vice versa. The signal can remain low for two
consecutive write cycles.
3.4.2 Function Codes
The CPU32 automatically generates function code signals FC[2:0]. The function codes can be consid-
ered address extensions that automatically select one of eight address spaces to which an address ap-
plies. These spaces are designated as either user or supervisor, and program or data spaces. Address
space 7 is designated CPU space. CPU space is used for control information not normally associated
with read or write bus cycles. Function codes are valid while AS is asserted.
3.4.3 Address Bus
Address bus signals ADDR[23:0] define the address of the most significant byte to be transferred during
a bus cycle. The MCU places the address on the bus at the beginning of a bus cycle. The address is
valid while AS is asserted.
Table 8 Size Signal Encoding
SIZ1
SIZ0
Transfer Size
0
1
Byte
1
0
Word
1
Three Byte
0
Long Word
Table 9 CPU32 Address Space Encoding
FC2
FC1
FC0
Address Space
0
Reserved
0
1
User Data Space
0
1
0
User Program Space
0
1
Reserved
1
0
Reserved
1
0
1
Supervisor Data Space
1
0
Supervisor Program Space
1
CPU Space
相关PDF资料
PDF描述
MC68331CFC25B1 32-BIT, 25 MHz, MICROCONTROLLER, PQFP132
MC68331CPV16B1 32-BIT, 16 MHz, MICROCONTROLLER, PQFP144
MC68331CPV20 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP144
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MC68331MFC16 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP132
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