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| 型号： | MC68332ACAG16 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 16 MHz, MICROCONTROLLER, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144 |
| 文件页数： | 82/109页 |
| 文件大小： | 787K |
| 代理商： | MC68332ACAG16 |
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MOTOROLA
MC68332
74
MC68332TS/D
SCK baud rate:
SCK Baud Rate = System Clock/(2SPBR)
or
SPBR = System Clock/(2SCK)(Baud Rate Desired)
where SPBR equals {2, 3, 4,..., 255}
Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its
inactive state value. No serial transfers occur. At reset, baud rate is initialized to one eighth of the sys-
tem clock frequency.
SPCR1 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write
this register, but the QSM has read access only, except for SPE, which is automatically cleared by the
QSPI after completing all serial transfers, or when a mode fault occurs.
SPE — QSPI Enable
0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O.
1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI.
DSCKL — Delay before SCK
When the DSCK bit in command RAM is set, this field determines the length of delay from PCS valid to
SCK transition. PCS can be any of the four peripheral chip-select pins. The following equation deter-
mines the actual delay before SCK:
PCS to SCK Delay = [DSCKL/System Clock]
where DSCKL equals {1, 2, 3,..., 127}.
When the DSCK value of a queue entry equals zero, then DSCKL is not used. Instead, the PCS valid-
to-SCK transition is one-half SCK period.
DTL — Length of Delay after Transfer
When the DT bit in command RAM is set, this field determines the length of delay after serial transfer.
The following equation is used to calculate the delay:
Delay after Transfer = [(32DTL)/System Clock]
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL causes a delay-after-transfer value of 8192/System Clock.
If DT equals zero, a standard delay is inserted.
Standard Delay after Transfer = [17/System Clock]
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted
between consecutive transfers to allow serial A/D converters to complete conversion.
SPCR1 — QSPI Control Register 1
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15
14
8
7
0
SPE
DSCKL
DTL
RESET:
0
1
0
1
0
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For More Information On This Product,
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相关代理商/技术参数 |
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|---|---|
| MC68332ACAG16 | 制造商:Freescale Semiconductor 功能描述:32-Bit Microcontroller IC |
| MC68332ACAG16B1 | 制造商:Freescale Semiconductor 功能描述: |
| MC68332ACAG20 | 功能描述:32位微控制器 - MCU 32B MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
| MC68332ACAG20 | 制造商:Freescale Semiconductor 功能描述:MICROCONTROLLER |
| MC68332ACAG25 | 功能描述:32位微控制器 - MCU 32B MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT |
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