参数资料
型号: MC68332ACAG20
厂商: Freescale Semiconductor
文件页数: 83/88页
文件大小: 0K
描述: IC MCU 32BIT 20MHZ 144-LQFP
标准包装: 60
系列: M683xx
核心处理器: CPU32
芯体尺寸: 32-位
速度: 20MHz
连通性: EBI/EMI,SCI,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 15
程序存储器类型: ROMless
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 144-LQFP
包装: 托盘
产品目录页面: 733 (CN2011-ZH PDF)
MOTOROLA
MC68332
84
MC68332TS/D
7 Standby RAM with TPU Emulation RAM
The TPURAM module contains a 2-Kbyte array of fast (two bus cycle) static RAM, which is especially
useful for system stacks and variable storage. Alternately, it can be used by the TPU as emulation RAM
for new timer algorithms.
7.1 Overview
The TPURAM can be mapped to any 4-Kbyte boundary in the address map, but must not overlap the
module control registers. (Overlap makes the registers inaccessible.) Data can be read or written in
bytes, word, or long words. TPURAM responds to both program and data space accesses. Data can be
read or written in bytes, words, or long words. The TPURAM is powered by VDD in normal operation.
During power-down, the TPURAM contents are maintained by power on standby voltage pin VSTBY.
Power switching between sources is automatic.
Access to the TPURAM array is controlled by the RASP field in TRAMMCR. This field can be encoded
so that TPURAM responds to both program and data space accesses. This allows code to be executed
from TPURAM, and permits the use of program counter relative addressing mode for operand fetches
from the array.
An address map of the TPURAM control registers follows. All TPURAM control registers are located in
supervisor data space.
Y = M111, where M is the logic state of the MM bit in the SIMCR.
7.2 TPURAM Register Block
There are three TPURAM control registers: the RAM module configuration register (TRAMMCR), the
RAM test register (TRAMTST), and the RAM array base address registers (TRAMBAR).
There is an 8-byte minimum register block size for the module. Unimplemented register addresses are
read as zeros, and writes have no effect.
7.3 TPURAM Registers
TSTOP —Stop Control
0 = RAM array operates normally.
1 = RAM array enters low-power stop mode.
This bit controls whether the RAM array is in stop mode or normal operation. Reset state is zero, for
normal operation. In stop mode, the array retains its contents, but cannot be read or written by the CPU.
Table 28 TPURAM Control Register Address Map
Access
Address
15
8 7
0
S
$YFFB00
TPURAM MODULE CONFIGURATION REGISTER (TRAMMCR)
S
$YFFB02
TPURAM TEST REGISTER (TRAMTST)
S
$YFFB04
TPURAM BASE ADDRESS REGISTER (TRAMBAR)
$YFFB06–
$YFFB3F
NOT USED
TRAMMCR —TPURAM Module Configuration Register
$YFFB00
15
14
13
12
11
10
9
8
7
0
STOP
0
RASP
NOT USED
RESET:
0
1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68332ACAG20 制造商:Freescale Semiconductor 功能描述:MICROCONTROLLER
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MC68332ACEH16B1 制造商:Freescale Semiconductor 功能描述: