参数资料
型号: MC68332ACEH16
厂商: Freescale Semiconductor
文件页数: 14/88页
文件大小: 0K
描述: IC MCU 32BIT 16MHZ 132-PQFP
标准包装: 36
系列: M683xx
核心处理器: CPU32
芯体尺寸: 32-位
速度: 16MHz
连通性: EBI/EMI,SCI,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 15
程序存储器类型: ROMless
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 132-BQFP 缓冲式
包装: 托盘
MC68332
MOTOROLA
MC68332TS/D
21
3.2.3 Bus Monitor
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The
monitor asserts BERR if response time is excessive.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a
system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
3.2.4 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhib-
ited by the HME bit in the SYPCR.
3.2.5 Spurious Interrupt Monitor
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-ac-
knowledge cycle.
3.2.6 Software Watchdog
The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that
a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watch-
dog times out and issues a reset. This register can be written at any time, but returns zeros when read.
Register shown with read value
Perform a software watchdog service sequence as follows:
a.
Write $55 to SWSR.
b.
Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be exe-
cuted between the two writes.
The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown
in the following table.
SWSR —Software Service Register
$YFFA27
15
8
7
6
5
4
3
2
1
0
NOT USED
0
RESET:
0
MODCLK
SWP
01
10
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC68332ACEH16 制造商:Freescale Semiconductor 功能描述:32-Bit Microcontroller IC
MC68332ACEH16B1 制造商:Freescale Semiconductor 功能描述:
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MC68332ACEH20 制造商:Freescale Semiconductor 功能描述:32-Bit Microcontroller IC
MC68332ACEH25 功能描述:32位微控制器 - MCU 32BIT MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 处理器系列:TMS320F28x 数据总线宽度:32 bit 最大时钟频率:90 MHz 程序存储器大小:64 KB 数据 RAM 大小:26 KB 片上 ADC:Yes 工作电源电压:2.97 V to 3.63 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:LQFP-80 安装风格:SMD/SMT