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| 型号： | MC68332ACFC20 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 19/88页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 20MHZ 132-PQFP |
| 标准包装： | 36 |
| 系列： | M683xx |
| 核心处理器： | CPU32 |
| 芯体尺寸： | 32-位 |
| 速度： | 20MHz |
| 连通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 15 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 132-BQFP 缓冲式 |
| 包装： | 托盘 |
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MOTOROLA
MC68332
26
MC68332TS/D
3.4 External Bus Interface
The external bus interface (EBI) transfers information between the internal MCU bus and external de-
vices. The external bus has 24 address lines and 16 data lines.
The EBI provides dynamic sizing between 8-bit and 16-bit data accesses. It supports byte, word, and
long-word transfers. Ports are accessed through the use of asynchronous cycles controlled by the data
transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). Multiple bus cycles
may be required for a transfer to or from an 8-bit port.
Port width is the maximum number of bits accepted or provided during a bus transfer. External devices
must follow the handshake protocol described below. Control signals indicate the beginning of the cycle,
the address space, the size of the transfer, and the type of cycle. The selected device controls the length
of the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity
of an address and provide timing information for data. The EBI operates in an asynchronous mode for
any port width.
To add flexibility and minimize the necessity for external logic, MCU chip-select logic can be synchro-
nized with EBI transfers. Chip-select logic can also provide internally-generated bus control signals for
these accesses. Refer to 3.5 Chip Selects for more information.
3.4.1 Bus Control Signals
The CPU initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the
beginning of the cycle, size signals SIZ0 and SIZ1 are driven along with the function code signals. The
size signals indicate the number of bytes remaining to be transferred during an operand cycle. They are
valid while the address strobe (AS) is asserted. The following table shows SIZ0 and SIZ1 encoding. The
read/write (R/W) signal determines the direction of the transfer during a bus cycle. This signal changes
state, when required, at the beginning of a bus cycle, and is valid while AS is asserted. R/W only chang-
es state when a write cycle is preceded by a read cycle or vice versa. The signal can remain low for two
consecutive write cycles.
3.4.2 Function Codes
The CPU32 automatically generates function code signals FC[2:0]. The function codes can be consid-
ered address extensions that automatically select one of eight address spaces to which an address ap-
plies. These spaces are designated as either user or supervisor, and program or data spaces. Address
space 7 is designated CPU space. CPU space is used for control information not normally associated
with read or write bus cycles. Function codes are valid while AS is asserted.
Table 8 Size Signal Encoding
SIZ1
SIZ0
Transfer Size
0
1
Byte
1
0
Word
1
Three Byte
0
Long Word
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