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| 型号： | MC68332ACFC25B1 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 25 MHz, MICROCONTROLLER, PQFP132 |
| 封装： | 0.950 X 0.950 INCH, 0.025 INCH PITCH, PLASTIC, QFP-132 |
| 文件页数： | 45/109页 |
| 文件大小： | 787K |
| 代理商： | MC68332ACFC25B1 |
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MOTOROLA
MC68332
40
MC68332TS/D
3.7.3 Reset Timing
The RESET input must be asserted for a specified minimum period in order for reset to occur. External
RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus
monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is
asserted, SIM pins are either in a disabled high-impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic clocks the signal into
an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after
it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset
to the entire system.
If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512
cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert
RESET until the internal reset signal is negated.
After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for ten cy-
cles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one,
reset exception processing begins. If, however, the reset input is at logic level zero, the reset control
logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-
impedance state for ten cycles, then it is tested again. The process repeats until RESET is released.
3.7.4 Power-On Reset
When the SIM clock synthesizer is used to generate the system clock, power-on reset involves special
circumstances related to application of system and clock synthesizer power. Regardless of clock
source, voltage must be applied to clock synthesizer power input pin VDDSYN in order for the MCU to
operate. The following discussion assumes that VDDSYN is applied before and during reset. This mini-
mizes crystal start-up time. When VDDSYN is applied at power-on, start-up time is affected by specific
crystal parameters and by oscillator circuit design. VDD ramp-up time also affects pin state during reset.
During power-on reset, an internal circuit in the SIM drives the internal (IMB) and external reset lines.
The circuit releases the internal reset line as VDD ramps up to the minimum specified value, and SIM
pins are initialized. When VDD reaches the specified minimum value, the clock synthesizer VCO begins
operation. Clock frequency ramps up to the specified limp mode frequency. The external RESET line
remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.
The SIM clock synthesizer provides clock signals to the other MCU modules. After the clock is running
and the internal reset signal is asserted for four clock cycles, these modules reset. VDD ramp time and
VCO frequency ramp time determine how long these four cycles take. Worst case is approximately 15
milliseconds. During this period, module port pins may be in an indeterminate state. While input-only
pins can be put in a known state by means of external pull-up resistors, external logic on input/output
or output-only pins must condition the lines during this time. Active drivers require high-impedance buff-
ers or isolation resistors to prevent conflict.
3.7.5 Use of Three State Control Pin
Asserting the three-state control (TSC) input causes the MCU to put all output drivers in an inactive,
high-impedance state. The signal must remain asserted for ten clock cycles in order for drivers to
change state. There are certain constraints on use of TSC during power-on reset:
When the internal clock synthesizer is used (MODCLK held high during reset), synthesizer ramp-
up time affects how long the ten cycles take. Worst case is approximately 20 milliseconds from TSC
assertion.
When an external clock signal is applied (MODCLK held low during reset), pins go to high-imped-
ance state as soon after TSC assertion as ten clock pulses have been applied to the EXTAL pin.
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