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参数资料
| 型号： | MC68332GVEH25 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 31/88页 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 25MHZ 132-PQFP |
| 标准包装： | 36 |
| 系列： | M683xx |
| 核心处理器： | CPU32 |
| 芯体尺寸： | 32-位 |
| 速度： | 25MHz |
| 连通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 15 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 2K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 132-BQFP 缓冲式 |
| 包装： | 托盘 |
| 产品目录页面： | 733 (CN2011-ZH PDF) |
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MC68332
MOTOROLA
MC68332TS/D
37
The bits in this register control the function of each port E pin. Any bit set to one configures the corre-
sponding pin as a bus control signal, with the function shown in the following table. Any bit cleared to
zero defines the corresponding pin to be an I/O pin, controlled by PORTE and DDRE.
Data bus bit 8 controls the state of this register following reset. If DATA8 is set to one during reset, the
register is set to $FF, which defines all port E pins as bus control signals. If DATA8 is cleared to zero
during reset, this register is set to $00, configuring all port E pins as I/O pins.
Any bit cleared to zero defines the corresponding pin to be an I/O pin. Any bit set to one defines the
corresponding pin to be a bus control signal.
The write to the port F data register is stored in the internal data latch, and if any port F pin is configured
as an output, the value stored for that bit is driven onto the pin. A read of the port F data register returns
the value at the pin only if the pin is configured as a discrete input. Otherwise, the value read is the value
stored in the register.
The port F data register is a single register that can be accessed in two locations. When accessed at
$YFFA19, the register is referred to as PORTF0; when accessed at $YFFA1B, the register is referred
to as PORTF1. The register can be read or written at any time. It is unaffected by reset.
The bits in this register control the direction of the pin drivers when the pins are configured for I/O. Any
bit in this register set to one configures the corresponding pin as an output. Any bit in this register
cleared to zero configures the corresponding pin as an input.
PEPAR — Port E Pin Assignment Register
$YFFA17
15
8
7
6
5
4
3
2
1
0
NOT USED
PEPA7
PEPA6
PEPA5
PEPA4
PEPA3
PEPA2
PEPA1
PEPA0
RESET:
DATA8
Table 16 Port E Pin Assignments
PEPAR Bit
Port E Signal
Bus Control Signal
PEPA7
PE7
SIZ1
PEPA6
PE6
SIZ0
PEPA5
PE5
AS
PEPA4
PE4
DS
PEPA3
PE3
RMC
PEPA2
PE2
AVEC
PEPA1
PE1
DSACK1
PEPA0
PE0
DSACK0
PORTF0, PORTF1 — Port F Data Register
$YFFA19, $YFFA1B
15
8
7
6
5
4
3
2
1
0
NOT USED
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
RESET:
U
DDRF — Port F Data Direction Register
$YFFA1D
15
8
7
6
5
4
3
2
1
0
NOT USED
DDF7
DDF6
DDF5
DDF4
DDF3
DDF2
DDF1
DDF0
RESET:
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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