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| 型号： | MC68711E20MFNE3 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 118/138页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 52-PLCC |
| 标准包装： | 23 |
| 系列： | HC11 |
| 核心处理器： | HC11 |
| 芯体尺寸： | 8-位 |
| 速度： | 4MHz |
| 连通性： | SCI，SPI |
| 外围设备： | POR，WDT |
| 输入/输出数： | 38 |
| 程序存储器容量： | 20KB（20K x 8） |
| 程序存储器类型： | OTP |
| EEPROM 大小： | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 数据转换器： | A/D 8x8b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 52-LCC（J 形引线） |
| 包装： | 管件 |
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Serial Peripheral Interface (SPI)
MC68HC711D3 Data Sheet, Rev. 2.1
80
Freescale Semiconductor
7.5.2 Master Out/Slave In (MOSI)
The MOSI line is the second of the two unidirectional serial data signals. It is an output from a master
device and an input to a slave device. The master device places data on the MOSI line a half-cycle before
the clock edge that the slave device uses to latch the data.
7.5.3 Serial Clock (SCK)
SCK, an input to a slave device, is generated by the master device and synchronizes data movement in
and out of the device through the MOSI and MISO lines. Master and slave devices are capable of
exchanging a byte of information during a sequence of eight clock cycles.
Four possible timing relationships can be chosen by using control bits CPOL and CPHA in the serial
peripheral control register (SPCR). Both master and slave devices must operate with the same timing.
The SPI clock rate select bits, SPR1 and SPR0, in the SPCR of the master device, select the clock rate.
In a slave device, SPR1 and SPR0 have no effect on the operation of the SPI.
7.5.4 Slave Select (SS)
The SS input of a slave device must be externally asserted before a master device can exchange data
with the slave device. SS must be low before data transactions and must stay low for the duration of the
transaction.
The SS line of the master must be held high. If it goes low, a mode fault error flag (MODF) is set in the
serial peripheral status register (SPSR). To disable the mode fault circuit, write a 1 in bit 5 of the port D
data direction register. This sets the SS pin to act as a general-purpose output. The other three lines are
dedicated to the SPI whenever the serial peripheral interface is on.
The state of the master and slave CPHA bits affects the operation of SS. CPHA settings should be
identical for master and slave. When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI message. When CPHA = 1, SS
can be left low between successive SPI characters. In cases where there is only one SPI slave MCU, its
SS line can be tied to VSS as long as only CPHA = 1 clock mode is used.
7.6 SPI System Errors
Two system errors can be detected by the SPI system. The first type of error arises in a multiple-master
system when more than one SPI device simultaneously tries to be a master. This error is called a mode
fault. The second type of error, write collision, indicates that an attempt was made to write data to the
SPDR while a transfer was in progress.
When the SPI system is configured as a master and the SS input line goes to active low, a mode fault
error has occurred — usually because two devices have attempted to act as master at the same time. In
cases where more than one device is concurrently configured as a master, there is a chance of contention
between two pin drivers. For push-pull CMOS drivers, this contention can cause permanent damage. The
mode fault attempts to protect the device by disabling the drivers. The MSTR control bit in the SPCR and
all four DDRD control bits associated with the SPI are cleared. An interrupt is generated subject to
masking by the SPIE control bit and the I bit in the CCR.
Other precautions may need to be taken to prevent driver damage. If two devices are made masters at
the same time, mode fault does not help protect either one unless one of them selects the other as slave.
The amount of damage possible depends on the length of time both devices attempt to act as master.
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相关代理商/技术参数 |
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|---|---|
| MC68711E20MFNE3R | 功能描述:IC MCU 8BIT 52-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 标准包装:1 系列:AVR® ATmega 核心处理器:AVR 芯体尺寸:8-位 速度:16MHz 连通性:I²C，SPI，UART/USART 外围设备:欠压检测/复位，POR，PWM，WDT 输入/输出数:32 程序存储器容量:32KB（16K x 16） 程序存储器类型:闪存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:44-TQFP 包装:剪切带 (CT) 其它名称:ATMEGA324P-B15AZCT |
| MC68711E20VFNE2 | 功能描述:8位微控制器 -MCU 8B 20K EPROM 768RAM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| MC6875 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:CLOCK GENERATOR/DRIVER (SCHOTTKY MONOLITHIC INTEGRATED CIRCUIT) |
| MC6875A | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:CLOCK GENERATOR/DRIVER (SCHOTTKY MONOLITHIC INTEGRATED CIRCUIT) |
| MC6875AL | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:CLOCK GENERATOR/DRIVER (SCHOTTKY MONOLITHIC INTEGRATED CIRCUIT) |
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