参数资料
型号: MC68EN360EM25
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 7 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP240
封装: PLASTIC, QFP-240
文件页数: 1/14页
文件大小: 47K
代理商: MC68EN360EM25
MOTOROLA
SEMICONDUCTOR
PRODUCT INFORMATION
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by MC68360D
MC68360
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without
notice.
MOTOROLA 1993
Product Brief
MC68360 QUad Integrated Communication
Controller (QUICC)
INTRODUCTION
The MC68360 QUad Integrated Communication Controller (QUICC
) is a versatile one-chip integrated
microprocessor and peripheral combination that can be used in a variety of controller applications. It
particularly excels in communications activities. The QUICC (pronounced “quick”) can be described as a
next-generation MC68302 with higher performance in all areas of device operation, increased flexibility,
major extensions in capability, and higher integration. The term "quad" comes from the fact that there are
four serial communications controllers (SCCs) on the device; however, there are actually seven serial
channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).
QUICC Key Features
The following list summarizes the key MC68360 QUICC features:
CPU32+ Processor (4.5 MIPS at 25 MHz)
— 32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)
— Background Debug Mode
— Byte-Misaligned Addressing
Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
Up to 32 Address Lines (At Least 28 Always Available)
Complete Static Design (0–25-MHz Operation)
Slave Mode To Disable CPU32+ (Allows Use with External Processors)
— Multiple QUICCs Can Share One System Bus (One Master)
— MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion
Chip and Intelligent Peripheral (22 MIPS at 25 MHz)
— Also Supports External MC68030-Type Bus Masters
— All QUICC Features Usable in Slave Mode
Memory Controller (Eight Banks)
— Contains Complete Dynamic Random-Access Memory (DRAM) Controller
— Each Bank Can Be a Chip Select or Support a DRAM Bank
— Up to 15 Wait States
— Glueless Interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random-Access
相关PDF资料
PDF描述
MC68EN360FE33 RISC MICROCONTROLLER, CQFP240
MC68360RC25 RISC MICROCONTROLLER, CPGA241
MC68EN360RC25 RISC MICROCONTROLLER, CPGA241
MC68360FE25 32-BIT, 25 MHz, RISC PROCESSOR, CQFP240
MC68360CFE25 RISC MICROCONTROLLER, CQFP240
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MC68EN360EM25K 制造商:Motorola Inc 功能描述:68EN360EM25K
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