
MC68HC05B6
Rev. 4.1
Freescale
E-27
MC68HC705B16
14
E.8
Control timing
Table E-11 Control timing for 5V operation
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
External clock option
fOSC
—
dc
4.2
MHz
Internal operating frequency (fOSC/2)
Using crystal
Using external clock
fOP
dc
2.1
MHz
480
—
ns
—
100
ms
Stop recovery start-up time (crystal oscillator)
tILCH
100
ms
RC oscillator stabilization time
tADRC
5
s
A/D converter stabilization time
tADON
500
s
External RESET input pulse width
tRL
1.5
—
tCYC
Power-on RESET output pulse width
4064 cycle
16 cycle
tPORL
4064
16
—
tCYC
Watchdog RESET output pulse width
tDOGL
1.5
—
tCYC
Watchdog time-out
tDOG
6144
7168
tCYC
EEPROM byte erase time
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (industrial)
– 40 to 125 (automotive)
tERA
10
—
ms
EEPROM byte program time(1)
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (industrial)
– 40 to 125 (automotive)
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
tPROG
10
15
20
—
ms
Resolution(2)
Input capture pulse width
Input capture pulse period
(2) Since a 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting
factor in determining the timer resolution.
tRESL
tTH, tTL
tTLTL
4
125
—(3)
(3) The minimum period tTLTL should not be less than the number of cycle times it takes to
execute the capture interrupt service routine plus 24 tCYC.
—
tCYC
ns
tCYC
Interrupt pulse width (edge-triggered)
tILIH
125
—
ns
Interrupt pulse period
tILIL
—(4)
(4) The minimum period tILIL should not be less than the number of cycle times it takes to
execute the interrupt service routine plus 21 tCYC.
—tCYC
OSC1 pulse width(5)
(5) tOH and tOL should not total less than 238ns.
tOH, tOL
90
—
ns
Write/Erase endurance(6)(7) (6) At a temperature of 85°C
—
10000
cycles
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
—
10
years