
MC68HC05B6
Rev. 4
MOTOROLA
E-19
MC68HC705B16
14
E.4.4
RAM parallel bootstrap
The program rst checks the state of the security bit. If the SEC bit is active, i.e. ‘0’, the program
will not enter the RAM bootstrap mode and the red LED will ash. Otherwise the RAM bootstrap
program will start loading the RAM with external data (e.g. from a 2564 or 2764 EPROM). Before
loading a new byte the state of the PD4/AN4 pin is checked. If this pin goes to level ‘0’, or if the
RAM is full, then control is given to the loaded program at address $0050. See
Figure E-3 and
If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6
according to
Figure E-9. If the data comes from an external EPROM, the handshake can be
disabled by connecting together PC5 and PC6.
Figure E-10 provides a schematic diagram of a circuit that can be used to load the RAM with short
test programs. Up to 8 programs can be loaded in turn from the EPROM. Selection is
accomplished by means of the switches connected to the EPROM higher address lines (A8
through A10). If the user program sets PC0 to level ‘1’, this will disable the external EPROM, thus
rendering both port A output and port B input available. The EPROM parallel bootstrap loader
schematic can also be used (Figure E-7), provided VPP is at VDD level. The high order address lines will be at zero. The LEDs will stay off.
Figure E-9 Parallel RAM loader timing diagram
tADR
tDHR
Address
Data
tCR
PD4
tEXR max
tHO
tHI max
PC5 out
PC6 in
tADR max (address to data delay; PC6=PC5)
16 machine cycles
tDHR min (data hold time)
4 machine cycles
tCR (load cycle time; PC6=PC5)
49 machine cycles
tHO (PC5 handshake out delay)
5 machine cycles
tHI max (PC6 handshake in, data hold time)
10 machine cycles
tEXR max (max delay for transition to be recognised during this cycle; PC6=PC5
30 machine cycles
1 machine cycle = 1/(2f0(Xtal))
TPG
203
05B6Book Page 19 Tuesday, April 6, 1999 8:24 am