参数资料
型号: MC68HC05C8AMP
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP40
封装: PLASTIC, DIP-40
文件页数: 107/166页
文件大小: 1914K
代理商: MC68HC05C8AMP
Interrupts
External Interrupt (IRQ)
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A — Rev. 5.0
Technical Data
MOTOROLA
Interrupts
45
4.5 External Interrupt (IRQ)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
IRQ. It is then synchronized internally and serviced as specified by the
contents of $1FFA and $1FFB.
When any of the port B pullups are enabled, that pin becomes an
additional external interrupt source which is coupled to the IRQ pin logic.
It follows the same edge/edge-level selection that the IRQ pin has. See
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-
only trigger operation is selectable by mask option.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I bit is cleared.
4.6 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $1FF8 and $1FF9.
4.7 Serial Communications Interrupt (SCI)
Five different SCI interrupt flags cause an SCI interrupt whenever they
are set and enabled. The interrupt flags are in the SCI status register
(SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$1FF6 and $1FF7.
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